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Tensilica upgrades Xtensa cores, tools

Posted: 28 Dec 2007 ?? ?Print Version ?Bookmark and Share

Keywords:Xtensa? configurable processor? MCUs?

Tensilica has new hardware options for its Xtensa 7 and Xtensa LX2 configurable processor families, as well as enhancements to its Xtensa Xplorer design environment. The enhancements shrink the minimum core size and make customization easier and faster.

The most significant new hardware option is a 16-entry register file in addition to the existing support for 32-entry and 64-entry configuration options. This option lets the 32bit Xtensa cores compete in area and power with 8bit and 16bit MCUs.

Xtensa also gains a multicycle, low-area 32x32 multiplier option that is more area efficient than the existing single-cycle 16bit and 32bit multiplier options. This new 32x32 multiplier is useful for high-precision applications like MP3 decoding. Other upgrades include relocatable vectors, an integer divider and an ARM AMBA AXI bridge.

The most important software enhancement is the automated Flexible Length Instruction Extension (FLIX) generator for Xtensa LX2, which profiles a designer's code and suggests VLIW (very long instruction word) instructions. Tensilica claims that designers can accelerate general purpose code between 40-60 percent by using simple, general purpose VLIW instructions. Using specially targeted VLIW instructions, the company claims designers have been able to quadruple processor performance.

Another interesting software enhancement is the "Manual Fusion Editor," a graphical tool that enables the designer to graphically create chains or "fusions" of operations to speed up code. For example, basic ADD and SHIFT operations can be combined to form an ADD_SHIFT instruction that executes in one cycle. This ADD_SHIFT instruction could replace two sequentially issued instructions (ADD followed by SHIFT), thus saving a clock cycle and saving code size.

Other software enhancements include: improved energy estimation through visualization and automatic cache energy search tools, a 15-30 percent speed up of the cycle-accurate instruction set simulator (ISS), and a new dynamic loader which allows binaries to be loaded in different memory addresses at runtime.

All enhancements are currently shipping with the cores from the Xtensa LX2 and Xtensa 7 families.

- Kenton Williston
DSP DesignLine




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