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Beat the SoC challenge with a tuner

Posted: 02 Jan 2008 ?? ?Print Version ?Bookmark and Share

Keywords:Cypress? integrated SoC design? tuner background debugger?

Custom integrated SoC designs are a great way to replace multiple individual ICs and support circuitry (as well as PCB space and traces). The benefits are many: you save space, power, and money. However, there is a challenge to overcome. Traditional (non-SoC) designs can be tested, probed and monitored during the design cycle with little advanced planning. Even when a circuit board does not have a required test point exposed, almost any technician can solder a test lead where needed. This is not the case once a design is captured into a highly integrated SoC. Debug and optimization late in the game can be extremely painful unless you have a strategy and built-in support.

Chipmakers have faced this problem for a long time, and we can take a page out of their playbook when we design our own custom IC. Typically, one of three methods is used: built-in test support vectors, a built-in command-driven supervisor, or a background debugger. The problem in using built-in test vectors is the design of suitable vectors.

Advises Jon Pearson of Cypress Semiconductor, you need to be very familiar with the expected behavior in order to define the vectors, so this approach is better for low-level testing of functions, rather than whole-system optimization. Using a built-in command-driven supervisor is better for SoC because it supports ad-hoc testing and debugging, which means you don't need to know exactly what you are looking for before you begin. The downside of a built-in command-driven supervisor approach is that the debugging is intrusive, thus you are not getting real-world, real-time behavior.

View the PDF document for more information.

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