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Actel FPGAs balance power, speed, cost

Posted: 09 Jan 2008 ?? ?Print Version ?Bookmark and Share

Keywords:flash-based FPGAs? Flash*Freeze? SRAM?

The folks at Actel have just introduced their ProASIC3L family of FPGAs for designers of high-performance, power-conscious systems.

Featuring 40 percent lower dynamic power and 90 percent lower static power than its previous-generation ProASIC3 FPGAs, the new flash-based family combines dramatically reduced power consumption with up to 350MHz operation. As a result, Actel says that designers in high-performance market segmentssuch as industrial, medical and scientificnow have access to flexible, feature-rich solutions that offer speed, low power and low cost.

Intelligent FPGAs
The ProASIC3L family also supports the free implementation of an FPGA-optimized 32bit ARM Cortex-M1 processor, allowing system designers to select the Actel flash-based FPGA solution that best meets their speed and power design requirements regardless of application or volume.

Dynamic power is critical in applications where clocks are constantly switching and providing input to an FPGA, such as high-speed data pipelines for portable video and medical appliances. Like the company's 5?W IGLOO FPGA family, the ProASIC3L devices support a 1.2V core voltage and Actel's innovative Flash*Freeze technology. Flash*Freeze enables designers to quickly switch the device from dynamic operation to static without switching off clocks or power supplies. Actel claims that in a typical high-speed design using comparable 1 million gate FPGAs, SRAM-based competitive solutions consume 60 percent higher dynamic power and 100x more static power than the ProASIC3L devices, which consume just 100mA of dynamic power and 1mW of static power.

Based on Actel's ProASIC3 architecture, the ProASIC3L family is comprised of four family members ranging from 250,000 to 3 million gates: the A3P250L, A3P600L, A3P1000L and A3PE3000L. Offered in both commercial and industrial temperature grades, the devices feature embedded SRAM memory, high I/O counts, phase-locked loops (PLLs) and nonvolatile memory.

Free of the license and royalty fees typically associated with industry-leading processor cores, Actel is initially offering the 32bit ARM Cortex-M1 processor for use in its 600,000-gate ProASIC3L device, the M1A3P600L. Operating at up to 70MHz and consuming 32 percent of available chip real estate, the highly configurable processor is said to provide a good balance between size and speed, while offering space for customization.

Tool support
The ProASIC3L family is supported by the Actel Libero IDE version 8.2. The Libero IDE includes sophisticated power-driven layout and analysis tools to further reduce dynamic power and provide users with a comprehensive understanding of power usage in all functional modes of a design. By using power-driven layout rather than timing-driven layout, system designers can reduce dynamic power by as much as 30 percent.

The Cortex-M1 processor is supported by both Actel and third-party toolsfrom compilers and debuggers to RTOS support. Actel supports the Cortex-M1 processor with the Actel Libero IDE as well as its CoreConsole and SoftConsole environmentsall available for free download from Actel's Website.

Actel will offer ProASIC3L and M1-enabled ProASIC3L starter kits to enable designers to evaluate quickly the family and prototype their low-power design. Detailed current-monitoring capabilities allow users to directly measure the low-current consumption and validate the design's performance when using ProASIC3L or M1-enabled ProASIC3L devices.

The ProASIC3L family is sampling now. Pricing for the ProASIC3L family, including the M1-enabled devices, starts at $3.95 in volume. The M1A3P600L will also be available in Q1 08 with the three remaining M1-enabled family members slated for Q2 and Q3. Version 8.2 of the Actel Libero IDE will be available this month. The two ProASIC3L starter kits will be available in Q1.

- Clive Maxfield
Programmable Logic DesignLine

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