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Using high-IF sampling ADCs beyond baseband frequencies

Posted: 10 Jan 2008 ?? ?Print Version ?Bookmark and Share

Keywords:ADC? baseband frequency? IF converter?

By Charles Sanna
Texas Instruments Inc.

In the simplest analog receive signal path, the antenna feeds an LNA, which in turn feeds an ADC, which then feeds a digital processor. In all but the least demanding of applications, the limitations of current technology keep this architecture on the engineer's mental blackboard rather than prototyped on a PCB. Typical ADC performance usually is limited to the first two Nyquist zones, confining the input frequency of the ADC to being less than the frequency of the sampling clock.

As a result, only the widest-bandwidth converters have the ability to sample at the lower end of the RF spectrum and, even then, with effective number of bits (ENOB) specification of eight bits or less. This falls well short of the needs of most applications, where the SNR and spurious free dynamic range (SFDR) requirements call for 10 to 12 effective bits.

To achieve the necessary SNR and SFDR performance, it is common for systems to convert RF frequencies at the antenna to low IF in the first Nyquist zone or even to baseband. This requires mixing stages with analog filters for the conversion, and an extra ADC, if the signal is converted to complex in-phase (I) and quadrature phase (Q) components. But the newest generation of high-speed pipeline converters gives the system designer the option of sampling large bandwidths at IF levels of 100MHz and higher, without sacrificing noise and linearity performance. This offers the ability to relax mixing stage requirements, or even remove one stage completely. With outputs of 12-, 14- and even 16bits, these ADCs still can provide the necessary ENOB at high IF levels.

Ten years ago, the fastest 14bit ADCs had maximum sample rates of around 40MSps. These parts were primarily designed to operate from DC to input frequencies up to half the sampling frequency, or the first Nyquist zone. Today, the fastest 14bit parts available can sample at around 210MSps, so the first Nyquist use can extend up to 105MHz.

Benefits to high-IF sampling
By going to a system architecture that takes advantage of the high IF abilities of today's ADCs, designers can reduce the number of components and, therefore, the physical size of the analog portion of the receive chain. Many systems wherein the ADC operates in first Nyquist zone use two mixing stages, with the first stage converting the information from RF to a high IF and the second converting down to the low IF or baseband, where the signal is sampled. By sampling at the high IF, the second mixing stage and the associated band-pass or low-pass filtering circuitry can be removed. For systems requiring multiple receive channels, this can save a large amount of board space, power and cost.

The other direct benefit of high-IF sampling converters in the analog domain is that they tend to have fast sampling rates. As sampling rate increases, so does the width of the Nyquist zones. This gives analog anti-aliasing filters (AAF) more room to transition from pass-band to suppression than with lower sampling-rate devices, easing the filtering requirements.

The large bandwidths typical of high-IF sampling ADCs also allow traditional analog hardware functions to be performed in the digital domain. In many communication systems, the incoming signal is split into I and Q channels, which forces the use of two ADCs. With high bandwidth and high IF converters, the signal can remain within a single channel through the converter and then be split and phase-shifted by subsequent digital circuitry, such as a digital down conversion (DDC) IC. By performing the quadrature demodulation in the digital domain, the split receive path is not needed, thus removing a converter, mixer and the requisite filtering from the architecture.

Another benefit of sampling at higher frequencies is that in systems where large bandwidths are not required, the high-IF sampling of the faster converters can be used to gain SNR performance using decimation. When decimating an ADC's output, you essentially throw away a periodic number of samples. Every time the output is decimated by a factor of two, where half the samples are removed, the SNR is improved by three dB. The cost is that the effective sample rate is now halved and, therefore, so is the available bandwidth.

For example, suppose a system requires only 20MHz of bandwidth, but the form factor needs to be small. It is possible with today's fastest 14bit ADC to sample this 20MHz of bandwidth at 200MSps with the center input frequency being 350MHz, a reasonable output for an RF-to-IF mixing stage. Choosing this frequency for the IF centers the signal band in the converter's Nyquist zone, which spans 300MHz to 400MHz. With the signal bandwidth residing in the 340-360MHz range, the AAF has 40MHz on either side of the signal to operate. From the contour plots in Figure 1, a converter can achieve 69dBFS SNR and 73dBc SFDR at this sample rate and input frequency.

Figure 1: Contour plots of SNR and SFDR versus input frequency for Texas Instruments' ADS5547

With only 20MHz of bandwidth to sample, a DDC's numerically controlled oscillator (NCO) could mix the signal to the I and Q bands. In turn, this allows the 200MSps sample rate to be decimated by a factor of four to an effective sample rate of 50MSps, increasing the SNR by 6dB to 75dBFS.

Increased signal-chain requirements for high-IF sampling
While implementing high-IF sampling solutions can lower component count and save board space, increasing the A/D input frequency does place more stringent demands on the analog signal chain than does low-IF sampling. In the above example, note that placing the center IF at 350MHz centers the bandwidth in a Nyquist zone and provides 40MHz of room for the AAF.

Although filtering a 20MHz band centered in a 100MHz Nyquist zone is generally easier than doing so in one which is 50MHz wide, doing so at 350MHz presents a challenge. Op amps tend to degrade in performance at such IF frequencies, so it may be necessary to build filtering from passive circuitry only, which is an inherently lossy implementation. Further, a lossy stage in the analog chain can limit system performance.

One of the main factors limiting the input frequencies, which can be sampled is the development of circuits to drive the input to today's ADCs, not just the limitations of the converters themselves. Input swings of 2VPP are typical for high-performance pipeline converters, and this strain is placed directly on the input buffer circuit. The input buffer usually consists of an op amp driving the full input swing to maximize SNR performance. But silicon-based op amps tend to have limited performance at higher IFs. These limitations directly affect the overall performance of the system.

Recent developments in SiGe material have allowed amplifier operating frequencies to push beyond silicon limitations. Currently, amplifiers are available that are designed to operate up to and beyond 350MHz. SiGe also has been used in some of the highest-performing ADCs and allows building a unity-gain buffer into the converter in front of the sample-and-hold circuit. This provides a high-impedance load to the external buffer stage, allowing easy implementation of buffer circuits with transformers when dc signals are not needed, or with amplifiers when DC is required.

In maximizing the performance of an ADC, clocking is of major importance, particularly for the achievable SNR. The maximum SNR that can be achieved by an ADC is limited by the combination of the internal jitters of both the converter and the input clock, Equation 1,

Equation 1

where the jitter is the combined rms of the two jitters.

As the input frequency to the converter increases, so does the requirement for clocking the converter. Today's converters can achieve SNRs approaching 70dB at input frequencies of 300MHz, with the limitation being the internal jitter of the ADC, known as aperture jitter. From the graph in Figure 2, we see that to achieve this SNR performance, the system jitter at the ADC must be lower than 200fs.

Figure 2: Maximum SNR possible versus input frequency for various system jitter performance

These "clean" clocking solutions may sound daunting, but it is possible to meet the jitter requirements with good clocking circuits built with VXCOs, clock-cleaning ICs, and passive crystal filters.

There are other potential issues in implementing high-IF sampling circuits, such as board trace layout and thermal effects, but these can be minimized when taken into account in system design. The highest-speed and highest-performance converters are more expensive and tend to consume more power than their lower-performing counterparts, both of which are tradeoffs that need to be weighed when deciding which architectural path to follow.

ADCs are not yet ready to be placed right on the antenna in demanding applications. But as technology progresses, ever faster- and better-performing pipeline converters will come to market, giving design engineers more and more flexibility in implementing high-IF sampling architectures to create systems which closely meet cost, size, and power budgets.

About the author
Charles Sanna
is a product marketing engineer for high-speed ADCs, Texas Instruments Inc.




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