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Address power management issues in mobiles

Posted: 21 Jan 2008 ?? ?Print Version ?Bookmark and Share

Keywords:power management? mobile phone? wireless application?

By Sabyasachi Dey
Texas Instruments

With the convergence of new computing, communication and entertainment applications on wireless handsets, power demands are increasing rapidly, however, the capacity of batteries cannot keep up. At the same time, consumers want sleek, compact mobile devices they can slip into a pocket.

Integration at the chip level?often combining multiple processing cores in the same device?and smaller, submicron fabrication processes help to reduce the size of wireless handsets while enabling added functionality. However, smaller submicron processes exacerbate the problem of static leakage power. Manufacturers of wireless handsets and other mobile devices are challenged to reduce power consumption while enhancing system performance. In other words, do more for less.

The rapid integration both in silicon and software space is posing a significant design problem for power management engineers. Power management no longer remains a hardware-only problem, rather it has become a system problem and being addressed by all engineers involved in system design process. Power management decisions are being taken at both hardware and software level. Techniques are invented and deployed in both hardware and software. Increasing focus towards system aspects of cellphones forces designers to take a holistic and dynamic approach to power management to effectively decrease power consumption without degrading performance.

A good number of techniques are used by designers to reach the goal?efficient processors, variable-speed clocks, circuit shutdowns, low-voltage logic, software design aids, and advanced power-management software (see Figure 1).

System-level power-management architecture typically starts with conservation at the source. For example, battery-management ICs and system-power regulators let engineers design power efficient products. Consider a typical wireless product with an RF receiver. Designers can employ a linear RF power controller to act as an on-off switch to conserve energy when the wireless feature is not in use. Effective power management architectures, however, must address all levels of system design. And software architecture plays a key role in system-level power management.

Silicon approach
Halving the supply voltage reduces power dissipation to one fourth (P=V^2/R). But reduced supply voltage coupled with faster clocks produce noise-immunity problems. New techniques are proposed to eliminate these low power-higher clock problems.

Texas Instruments has introduced the low voltage CMOS (AVC) logic family, which operates on supplies of 3.3-, 2.5-, or 1.8V with propagation delays of approximately 2ns. Digital logic blocks continue to function at even lesser voltages reducing overall system power consumption.

Digital designers are already implementing microprocessors in ultra-deep-submicron (130-, 90- and 65nm) processes, where they have found that the thinner oxides and smaller channel lengths yield fast transistors. Likewise, analog baseband and RF designers are following a path of integration to provide a single-chip wireless solution to their end customers. Voltage scaling has not kept up with oxide scaling, however, which has resulted in leaky system solutions?a definite drain on battery lifetime. Fortunately, there are some power-management techniques that can be used to lower power losses in single-chip solutions.

There are three identifiable forms of power supply drain:

  • Active current consumption

  • Standby current consumption (sometimes referred to as "sleep mode").
  • Off-mode current leakage.

    In the active mode, the dissipated power is a summation of both static bias current power dissipation and the average of switched or clocked (dynamic) power dissipation. Standby is a low-power state where most, if not all, of the dynamic power dissipation is absent because the clocks have been gated or turned off. In this mode, the magnitude of the static quiescent current dictates battery lifetime. The third form, off-mode power dissipation, is a function of the subthreshold leakage that the transistors in the chip exhibit when the chip is off, but when the input supply is still present.

    Figure 1: Different power management techniques.

    If ultradeep-submicron CMOS processes were able to handle the higher voltages of the battery (4.3V to 5.4V), the off-mode leakage would be negligible as effective channel lengths would be longer and the gate oxides thicker. Likewise, the active power-supply drain would be reduced, because such a process would be slow in terms of frequency, and dynamic power dissipation is a function of capacitance, frequency and input supply. Thus, one needs to address the matter of direct battery hookup of the power-management circuits. The two most commonly used circuits that can accomplish this with some modification are the low dropout regulator and the DC/DC buck switching regulator.

    Processors are also a key element in cellphone SoCs. Processor designers offer a host of power-management features that can be used to optimize power dissipation.

    Several types of wait, idle, standby, and sleep modes suspend processor operation during periods of inactivity. The trade-off is how quickly the processor can resume operation when called back to action. Designers also incorporate automatic power-saving features into their processors' architectures. By gating the clock, CPU designers can reduce the power to even a single register. System power directly relates to CPU clock speed. Many CPUs runs at a variable speed clock, allowing designers to adjust the frequency for optimal power savings. Some designers use the variable clock speed to dynamically control the clock rate and, therefore, power consumption from software. The program can increase the CPU clock speed when processing demands are high and then throttle back to a lower speed for non-critical tasks.

    Software technique
    Digital processors use CMOS-based circuits; they consume power mainly during switching from logic true to false, or vice versa. The switching power is proportional to the clock frequency and the square of the supply voltage. Therefore, lowering clock frequencies or supply voltages reduces power consumption. The mechanism of changing voltage or frequency is commonly known as "dynamic voltage" or "frequency scaling."

    Dynamic voltage scaling (DVS) has been widely deployed for microprocessors to achieve significant power savings. DVS in microprocessors exploit the variance in processor utilization, lowering the frequency (and voltage) when the processor is lightly loaded, and running at maximum frequency (and voltage) when the processor is heavily executing. Dynamic voltage and frequency scaling is increasingly being used to reduce the energy requirements of embedded and real-time applications by exploiting idle CPU resources, while still maintaining all application's real-time characteristics. Accurate prediction of task run-times is key to computing the frequencies and voltages that ensure that all tasks' real-time constraints are met.

    Many software power management algorithms achieves design goal by implementing some form of voltage or frequency scaling in conjunction with hardware support.

    Optimal embedded power savings result from an integrated software-management plan that controls system, CPU, and peripheral devices. Two standards-based approaches, Advanced Power Management and Advanced Configuration and Power Interface (ACPI), support power management in PCs but don't address the specific requirements of mobile devices.

    Advanced Configuration and Power Interface (ACPI), introduced in 1997 for desktop and notebook PCs in, puts the responsibility for power management on the OS. The OS is aware of new applications, and it has the data to make power-management decisions. Although ACPI targets desktops and notebooks, it makes a good model to follow when developing a software based power management system for embedded systems.

    With ACPI, software automatically controls the power to peripherals, and peripherals can also activate the processor. For example, receiving an incoming call with a modem powers the processor from standby mode in time to capture the data. This aggressive power management greatly increases battery life on portable embedded devices.

    ACPI defines a series of reduced-power states for the system, processor, and peripheral devices. When the system has been idle for a specified amount of time, the software enters system power-management, or sleep, states. The CPU does no work in any of the sleep states. The ACPI specification defines four levels of sleep states, each with increased power savings but requiring more time to resume. For example, if the software saves the contents of memory to disk in a level-four sleep state, the CPU takes several seconds to power up the disk and reload memory before resuming operation.

    An ACPI-compliant CPU has three power-management, or "C," states that require little time for entry and exit. State C1, the halt instruction, requires almost no time for the CPU to restart. C2 and C3 consume less power but take longer to resume. Intel reports that a 233MHz mobile Pentium II processor consumes 0.5W in state C2 and takes 10ms to resume. The same processor uses 0.15W in state C3 but needs 65ms to restart.

    The CPU can enter C states during the idle time between operator keystrokes to save considerable power. The ACPI specification also defines four "D" states that allow the operating system to manage the power consumption in devices and peripheral chips. The D states have different meanings, depending on the type of device. For example, a modem driver may specify D0 for full power, D2 for a 2-sec maximum restore time, and D3 for a 5-sec maximum restore time. Effective use of D states influences hardware design because peripheral power-down occurs at different times.

    Unified power
    Traditional power management techniques as described above have commonly been implemented in wireless handsets, PDAs, laptop computers and other power-sensitive devices. These techniques will continue to be applied, but the industry's current trends necessitate comprehensive and aggressive solutions that address both power and performance.

    For high performance, power-sensitive applications, power reduction is only half the challenge. The imperative today and moving into the future is to provide higher performance but consuming less power per function. The sophisticated applications that are converging on mobile handsets operate at much higher frequencies than voice communications. For example, simple audio on a wireless mobile device typically operates at less than 20MHz, whereas a video application may require a frequency of 200MHz or more. Just managing the hundreds of thousands of pixels in a high-resolution video display generates a tremendous amount of power-consuming processing cycles. Only creative new power reduction techniques that cross functional blocks and include multiple processing cores will allow the system to adapt itself dynamically to achieve high performance with less power.

    System-level method
    Dynamic power management may not be enough to meet the goal of delivering maximal performance at minimal power. TI's SmartReflex technology offers a system-wide perspective by optimizing power consumption at different levels, offering maximal performance at minimal power drain.

    SmartReflex technologies are comprised of three facets: silicon intellectual property; techniques that can be applied at the SoC design level; and system software that manages many of the hardware-enabled SmartReflex technologies, which interface seamlessly to other power management techniques based in OS or third-party software subsystems (see Figure 2).

    The first- and second-generation power management solutions were, by and large, vendor-specific and could only be applied to certain functional blocks or specific cores. As a result, they only address a small portion of the device's power budget. In contrast, SmartReflex technologies support multiple cores, hardware accelerators, functional blocks, peripherals and other system components. In addition, SmartReflex system-level technologies are open to OS-based and high level power management algorithms so that a collaborative and co-operative environment with regards to power and performance can be developed.

    Figure 2: SmartReflex technology

    A radio interface driven and application optimized high-level algorithm will perfectly complement such a technology and build a strong and effective power management system. For example, a methodology can be developed for GSM phones where modem specific hardware domains will go idle when the phone is in "GSM idle" mode and will come back to active state when the phone will enter into "GSM dedicated" mode. Depending on the radio interface and applications (camera preview or MP3 player) requirements, various sleep states can be defined. An efficient state transition logic with such states defined coupled with a system-level foundation like the SmartReflex can solve many power management problems and provide system designers a peace of mind.

    The forces in the marketplace do not rest. Wireless mobile devices and other battery operated portable systems must aggressively add new functionality and applications to meet ever growing user needs. Popular styles and new industrial designs will change the form factors that mobile devices come in, driving chips toward higher integration and smaller process geometries.

    Newer standards in wireless radio communication coupled with user demands will see numerous new devices in the marketplace. Some of them even will be reconfigurable in narute, such as software defined radio. Surely power management will become a more complex problem for such devices. A holistic system-wide approach to the problem is the key to solving it. Thankfully people at every facets of the industry and academia are concerned about power consumption issues and constantly working towards this. Right from modulation algorithm designers to user interface designers everyone is aware of saving last drop of power while delivering the best performance. This focus will bring in new architectures and solutions for power management in mobile devices sooner in future.

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