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Nanochip cooks up terabyte memory ICs

Posted: 29 Jan 2008 ?? ?Print Version ?Bookmark and Share

Keywords:terabyte memory chip? DRAM? MEMS?

Nanochip Inc. disclosed it is on-track on the development of terabyte memory chips, which combine phase-change media to cantilever read/write heads controlled by MEMS.

The memory chips will use conventional, DRAM-like interfaces but internally will function like a multiple-head hard drive, where slaved MEMS cantilevers will move in unison over their array of bit cells to read and write phase-change media. The company claims its first prototypes will be delivered in 2009, with volume production scheduled to 2010.

"We are well on-track to meet our original schedule of reaching full commercialization of our first product offering by 2010," said Gordon Knight, CEO of Nanochip.

Nanochip's potential bit cell size measures 2nm x 3nm, accounting for its terabyte-per-chip goal. Initial prototypes will have bit cells measuring about 15nm x 15nm for capacities around 100Gbyte per chip in 2010.

The company estimates it will be able to double capacity every year thereafter without scaling down the relaxed 1? geometry of their process. Instead, it will seek to improve the media and refining control of the ganged MEMS cantilever read/write heads.

"Nanochip's technology is well positioned to provide memory capacity with exponentially higher storage densities at a cost per gigabyte significantly below that of flash technology," said Keith Larson, VP and director of manufacturing, memory and digital health at Intel Capital.

- R. Colin Johnson
EE Times




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