Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Interfacing FPGAs to DDR3 SDRAM

Posted: 01 Feb 2008 ?? ?Print Version ?Bookmark and Share

Keywords:DDR3 SDRAM memory architectures? DIMM? FPGA?

DDR3 SDRAM architectures support higher bandwidths with bus rates of 600Mbit/s to 1.6Gbit/s (300-800MHz), 1.5V operation for lower power, and higher densities of 2Gbits on a 90nm process. While this architecture is undoubtedly faster, larger, and lower power per bit, how is the interface between a DDR3 SDRAM DIMM to an FPGA accomplished?

The key wordleveling.

Without the leveling feature designed directly into the FPGA I/O structure, interfacing anything to a DDR3 SDRAM DIMM is complicated, costly, and involves numerous external components including delay lines and associated controls.

To improve signal integrity when supporting higher frequencies, the JEDEC committee defined a fly-by termination scheme used with the clocks and the command/address bus signals to improve overall signal integrity in support of higher performance. Fly-by topology reduces the simultaneous switching noise (SSN) by deliberately causing flight-time skew between clock and data/strobes at every DRAM as the clock and address/command signals traverse the DIMM.

According to Altera's Paul Evans, FPGAs provide I/Os capable of speeds up to 400MHz (800Mbit/s) and have greater flexibility to support existing and emerging external memory standards such as DDR3.

View the PDF document for more information.

Article Comments - Interfacing FPGAs to DDR3 SDRAM
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top