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ARC pushes mobile multimedia SoC design

Posted: 01 Feb 2008 ?? ?Print Version ?Bookmark and Share

Keywords:development platform? mobile multimedia? design? IP core?

Schlachte: Need persists for configurability.

Configurable-core developer ARC International is refining a development platform that it says will change the way mobile multimedia systems are designed. ARC technologists described elements of the platform during the company's ConfigCon development conference last December.

The company also announced an initiative that offers startups up to $1 million in seed funding. The initiative is a collaboration with some venture capital groups and is targeted at companies developing multimedia applications using ARC tools or IP cores.

"I have already been approached here today by three people who want to apply, and we expect many more. And I would be really pleased if we end up supporting two really good ideasmaybe even just one outstanding one," said Carl Schlachte, ARC president and CEO.

Also at the conference, Jeff Hoffman, systems architect at Intel Corp.'s communications laboratory, gave further details of an experimental PHY chip that would "enable any mobile Internet device to connect to any network." The test SoC, based on an ARC 605+ core, initially supports 802.11n Wi-Fi, mobile WiMax and the DVB-H flavor of mobile TV. It is being taped out on a TSMC low-power 65nm process.

"It is not quite the Holy Grail of wireless connectivity, but we believe it is getting near the vision needed for devising next-generation radios for wireless," Hoffman said.

ARC executives said the integrated system design platform effort would not have yielded strategic benefits without the involvement of three acquisitions the company made in 2007: Tenison Technology EDA Ltd, which focuses on modeling, simulation and verification products to predict critical metrics of an SoC before the design is sent for manufacture; Teja Technologies, which has brought tools and multicore software platforms to market; and Alarity, which develops codec software, firmware and multimedia architectures.

Maximizing parallelism
"There are tactical benefits from our approachfor instance, enabling users to build a system much faster. But the strategic benefits are perhaps even more important," said Akash Deshpande, a member of the office of the chief technology officer at ARC and the founder of Teja. "It will bring benefits in terms of flexibility, scalability and turnaround time, as well as leverage IP across multiple products and projects. It also solves the incompatibility problem between portability and performance."

The project and platform "push the envelope in multiple technology directions to extract maximum parallelism, optimizing hardware and software together and creating a way to achieve engineering trade-offs," Deshpande said. "In basic terms, our idea is a mapping-driven implementation," he said. "We prescribe an API that the application software must use. If you write your application with such an API embedded, then that deals with access to the hardware, sorts out how you split things up and how to scale things. In essence, you do not need a software library. "The second phase is that you describe the hardware architecture in another API. The third component is a mapping system to bind it all together." Deshpande said "several of the largest semiconductor companies are already using elements of these technologies in their product development" but did not identify them.

Schlachte, in his keynote, referred several times to the discontinuity that has become so crucial to companies designing chips using the company's cores, notably in the consumer electronics space. "We as an industry are now looking at a development cycle for an end-user product that is typically 18 months and that often has a nine-month product introduction window," he said. "If theyor we as chip designers, or the foundryget the time scales wrong, our customer is looking at potentially huge inventory losses."

At a separate briefing, Schlachte acknowledged it has taken awhile for ARC to elaborate its advantages when it comes to configurability and design flow. "The changes we started a couple of years ago are now [coming] to fruition. We have the right answers, we have made the right acquisitions, and their impact can finally be seen in this design process we are pushing."

Asked whether configurability has had its day and may perhaps even be "dead," Schlachte said such is not the case. "At some level, you have to be able to deliver a suite of technologies to the chip and box guys that allow them to take care of all the standards and the level of differentiation they want. That is what configurability is about." A few years ago, "there may have been issues," he said. Today, "we may not have 100 percent of the solutions, but we are getting there and can address most concerns regarding differentiation and time-to-market, as witnessed by our announcements on these design methodologies and platform."

Schlachte conceded that ARC has "abstracted the message away from configurability, even if that is in essence what we do. But the end user really does not care what the term is, as long as the solutions are the right ones."

- John Walko
EE Times Europe

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