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IBM seeks standard to link chip models with tools

Posted: 04 Feb 2008 ?? ?Print Version ?Bookmark and Share

Keywords:interface standard? chip model? design tools?

An IBM executive has called for standards to link chip models with simulation tools in an effort to lower design costs and shorten time-to-market. The group IBM leads is about to start an internal effort to define such a standard for cores used in Power CPU-based designs.

The call came at a seminar on design virtualization hosted by Vast Systems Technology in the U.S state of California. At the event, speakers agreed engineers need to use virtual platforms to shrink design time and cost, but they indicated the emerging methodology still has many holes, including a lack of cost and energy models.

"We develop models for our cores within IBM, but for the design process to be effective we need to get these models into the proprietary tools of companies such as Vast and others," said Michael Paczan, chief technology officer of and a former lead Power PC designer at IBM. "That's where we need interface standards," he added, speaking on a panel at the event.

"Within the group we are in the process of defining the scope of a new technical subcommittee in modeling and virtual prototyping," said Paczan." In the next 45 days this subcommittee will start defining interfaces to allow interoperability between tools and portability of models between them," he said.

Last year, Vast made a proposal to the group on the issue, Paczan said. The group aims to embrace the work of new tool vendors such as Virtutech as well as other efforts based on SystemC and many other existing models and tools from other vendors.

"People have an installed base of tools and models they can't just throw away, so standards have to try to work with them all," said Paczan.

Accurate, high-speed models
Speakers at the event said engineers need to move to a new model where hardware and software are developed in parallel using accurate, high-speed models at the chip and even the system level. Several dynamics are driving the new direction.

"There is massive complexity today when cellphones are as complex as desktop PCs were 10 years ago," said Paczan. Virtual prototyping is "the only economical way in which you can build systems," he added.

Shifting from design based on a more linear model where hardware engineers hand off their work to software developers will take time, said Mark McDermott, a professor of engineering at the University of Texas in Austin who was also on the panel, "It can take a couple generations of engineers to change a design mindset," McDermott said.

McDermott and others praised the tools from Vast and others that are giving engineers choice in modeling more processor types at greater speeds than has been possible with other methods such as dropping a CPU core into an FPGA design flow. However, there are still gaps in the emerging approach of using virtual prototyping.

"One thing we are missing is accurate cost models," said McDermott who developed SoCs at Intel Corp. and Motorola Inc. "The software can still kill us because we have no idea how long it will take to develop," he added.

Missing energy models
In a world increasingly driven by mobile systems, energy models are also missing, said Grant Martin, chief scientist with Tensilica Inc. who attended the event.

"We are much farther behind in this area," Martin said. "We have done some things with energy modeling for our devices at Tensilica, but you really need to know about the energy models for other devices in a systemso we need lots of friends," he added.

Paczan pointed to the complexity of three major ASICs in the Playstation3 as an example that shows system-wide models are needed for virtual prototyping.

"I'd also like to see these tools get into mechatronics because there will be a lot of work ahead in sensor networks and robotics," said McDermott.

- Rick Merritt
EE Times

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