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Memory compiler optimized for UMC 65nm LL process

Posted: 06 Feb 2008 ?? ?Print Version ?Bookmark and Share

Keywords:memory complier? UMC LL process? 65nm node?

Faraday Technology Corp. has announced the availability of a memory compiler for UMC 65nm LL process. The 65nm LL memory solution features row redundancy, BIST test interface (BTI) and programmable sensing margin for manufacturing yield, and full-chip routability enhancement. The 65nm LL memory compiler is silicon-proven and is now available to customers.

Due to higher costs associated with 65nm, applications will be targeted at the mainstream market, such as wireless, consumer electronics, HD video/image and PON. These applications involve complex SoC design and can use hundreds of memories for video/network data processing. The use of 65nm technology provides good memory density. However, due to process variation and higher design complexity, the magnitude of memory leakage, yield loss and wiring congestion become major concerns for designers. With experienced memory design capability, DFM and power-aware design methodology, Faraday is able to deliver new features in the 65nm memory compiler to address these challenges.

"We are very glad to provide the first memory compiler in UMC 65nm LL process," said Hsin Wang, VP of sales at Faraday. "The repairable and low-leakage memory solution is designed for 65nm SoC that demands high density and low power. It enables our customers to be competitive on the market with lower power consumption, smaller size and higher level of integration. To date, three customers are designing in Faraday's new 65nm memory solution," he added.

Faraday's 65nm memory compiler is optimized for UMC's low-leakage process. It allows users to generate a variety of memory options, including words, bits and aspect ratios, while retaining desirable area, performance and power specification. A 4Kx16 memory provides 20-40 percent less the leakage ratio of 90nm SP with 50 percent area reduction and 20 percent performance improvement. In addition, Faraday memory compiler provides optimized features for DFM. Built-in two-row redundancy and programmable sensing margin are implemented for yield improvement. To facilitate chip-level integration, an optional BTI is provided for better routability, which will also reduce overall chip size by eliminating the use of memory routing channel.

"Migrating to the deep submicron process, memory design is becoming more complicated due to the device variability and increased array redundancy," said Victor Lin, VP of IP R&D and project at Faraday. "The new 65nm LL memory compiler keeps a high level of memory yield and reliability. In addition, its built-in function options and programmability allow easy design integration for our customers."

The memory compiler for UMC 65nm LL process is already available. High-speed version for performance SoC will be available in Q3 08.

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