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GDDR5 gears for bandwidth-hungry graphics

Posted: 11 Feb 2008 ?? ?Print Version ?Bookmark and Share

Keywords:high-end PC graphics? GDDR5? GDDR3? graphics DRAM?

By Christoph Bilger
Qimonda

While GDDR3 presently holds a share of about 90 percent of the high-end PC graphics market, the mainstream memory technology in 2011 for this segment is eyed to be GDDR5. The GDDR5 technology is targeted to become the next predominant graphics DRAM standard and is eyed to boost memory bandwidth of graphics applications to a new dimension.

For 2011, Mercury Research expects GDDR5 to capture 90 percent of the high-end graphics DRAM market, which then will feature a volume of $1.49 billion for PC applications alone. GDDR5 target applications include PC graphics solutions, game consoles, high-end consumer applications (DTV, STBs) and networking.

Future standard
Memory bandwidth is a key factor in the rapidly increasing 3D rendering performance of PC graphics systems and game consoles. The memory bandwidth of graphics DRAMs grows by 30 percent per year. The GDDR5 standard is about to get finalized in JEDEC. GDDR5 will be available with data rates up to 20GBps per component, which is more than double the bandwidth of the fastest GDDR3 memories today and comes with a multitude of advanced power saving features.

GDDR5 combines three basic concepts to ensure higher performance, stable system operation, low implementation costs and power efficiency. These include: improved signal integrity using data/address bit inversion, adjustable driver strengths, voltages and termination; adaptive interface timing with scalable data training; error compensation with real-time error detection. These features results in fast interface tweaking, reduced PCB costs, no trace length matching and more stable system operation.

Figure 1
(Click to view image.)

The Qimonda GDDR5 SGRAMs extend the reliable single-ended signaling concept of previous graphics standards to very high frequencies. GDDR5 continues the proven termination concept of high level termination, whereas voltage levels of Vdd and Vddq are as low as 1.5V, with an option for further voltage reductions. The GDDR5 interface is optimized for systems with 32bit or 64bit channels. Clocks, commands and addresses may be shared between two devices, while DQs are routed point-to-point to ensure the high data rates.

Bus inversion
Data bus inversion (DBI) is a technique to reduce the number of zeros that are transmitted. The data is inverted if more than 50 percent of the data bits within a byte are zeros. Since the GDDR5 transmission lines have high level termination, reducing the amount of signal lines driving a low level (zero) results in reduced power dissipation in the termination resistors and output drivers.

Additionally, data inversion improves the signal quality by reducing the supply noise-induced jitter on the data lines. GDDR5 provides address bus inversion (ABI) in the same fashion as DBI which reduces power consumption and noise on the address lines as well.

Figure 2(Click to view image.)

Signal training
Signal alignment is one of the challenges in high speed applications. The GDDR5 signal training concept provides an easy to implement and reliable solution to system builders. The GDDR5 signal training concept offers the possibility to train several signals and clocks relative to each other. Training means phase adjustment of the various signals.

GDDR5 operates with two different clock types: Command Clock (CK) to where address and command inputs are referenced, and Write Clock (WCK) where Read and Write data are referenced to. GDDR5 clock and data training is performed in three steps: Address training (aligns the address bus to the CK clock), Write clock (WCK) to clock (CK) alignment (adjusts the WCK clock to the CK clock at the DRAM's internal phase detector) and data training (finally aligns the data with the respective WCK clock). As a result of the training procedure, all signals and clocks are aligned in the memory as shown in Figure 3.

Perfect adaption
GDDR5 SGRAMs offer several features that let the controller perfectly adapt the device's I/O characteristics to the actual system impedance and thus, improve the data eye for a reliable data transmission:

  • auto calibration for process, voltage and temperature drift compensation

  • software-controlled adjustable drive strengths

  • software-controlled adjustable data, address and command termination impedances

  • software-controlled adjustable data input reference voltage

Error detection
A new feature of GDDR5 is the capability for detection of transmission errors occurring on the high speed signal lines. As graphics systems store increasingly more code in the DRAM, error detection becomes essential, as random bit fails associated with any high-speed data transmission would lead to unacceptable system failures.

Figure 3
(Click to view image.)

In GDDR5, the transmitted data is secured via CRC (cycle redundancy check) using an algorithm that is well established within high quality communication environments like ATM networks. The algorithm detects all single and double errors with 100 percent probability. When the DRAM controller detects an error, the command that caused the error can be repeated. Error detection can be used to trigger re-training of the data transmission line, which allows the system to dynamically adapt to changing conditions like temperature and voltage drift.

Memory core
The GDDR5 core architecture is optimized to sustain the high interface bandwidth of GDDR5 and in parallel ensure low latency random access throughout the core. This is achieved by having up to 16 banks and a prefetch of 8, which makes GDDR5 a high performance standard. The basic core parameters are 8 banks for 512Mbit GDDR5 and 16 banks for 1- or 2Gbit, prefetch of 8 and fixed page size for all densities of 2Kbytes.

Power management
GDDR5 is designed in a way to only consume power when really needed. Several features and methods are implemented in a way to allow a demand driven power management:

  • Extremely wide clock frequency range and data rates

  • Multi level, demand driven termination enabling

  • Low power modes for DRAM core

  • Low supply voltage of 1.5V

  • Data and address bit inversion

  • Power-down and self refresh modes

GDDR5 allows the system to dynamically scale the memory I/O data rate according to the workload. The I/O data rate of GDDR5 can be varied from 5Gbit/s down to 200Mbit/s (50MHz clock frequency). While going down the frequency path, a variety of operation parameters can get changed to operate always with the lowest possible power consumption.

For lower frequencies the PLL can get turned off and the GDDR5 interface can be set to a low power strobe mode. In this case, the GPU can turn off the clock data recovery reducing the power consumption. For data alignment in the strobe mode, the DRAM sends out a strobe signal via the EDC pins together with the data.

In addition to the I/O frequency scaling, the GDDR5 DRAM core offers a low power mode for operation at lower frequencies. The low power mode is initiated by a low power bit, which is set from the controller.

Signal termination is necessary to match impedances of transmission lines and improve signal quality. But termination consumes also power. At lower data rates, the signaling gains more and more margin, which allows to run the system with partially matched termination impedance. GDDR5 doubles the termination impedance for slower data rates or even turn it off. Termination can be adjusted separately for data bus, command and address bus and WCK clock to take maximum advantage of the power saving potential.

The data and address bit inversion feature does reduce the power consumed by the termination resistors and output drivers. The GDDR5 high level termination scheme only consumes power if the transmission line is driven to Low. As data and address bit inversion effectively reduces the amount of LOW signals on the data and address bus, it reduces the average power consumption as well.

About the author
Christoph Bilger
is a senior marketing manager at business unit graphics at Qimonda.




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