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USB IP saves power, simplifies connection

Posted: 12 Feb 2008 ?? ?Print Version ?Bookmark and Share

Keywords:USB IP? high-speed inter-chip? link power management?

Synopsys Inc. has expanded it DesignWare USB IP product line with support for the USB 2.0 Link Power Management (LPM) and High Speed Inter-Chip (HSIC) standards.

The new DesignWare USB LPM and HSIC digital controller and PHY IP reduce power consumption and area for USB-enabled chips. Both IP products leverage Synopsys' know-how in low power design methodology and tools to enable more power efficient ICs.

The DesignWare USB LPM IP digital controller and PHY IP implement a new power sleep state to reduce power consumption. The USB LPM IP can provide faster suspend and resume times by three orders of magnitude (now microseconds instead of milliseconds) compared to the existing USB 2.0 specification, allowing devices to save power by more frequently turning off the USB connection while idle. The DesignWare USB LPM IP is designed to further reduce power consumption over the existing low power DesignWare USB 2.0 IP architecture. The current DesignWare Hi-Speed USB On-the-Go digital controller IP implements multiple power domains, allowing nearly the entire core to be completely turned off while idle. This maximizes battery life with reduced leakage power by 95 percent compared to solutions that do not employ multiple power domains.

Meanwhile, the DesignWare HSIC digital controller and PHY IP eliminates USB cables and connectors, and simplifies the connection down to two wires for high speed chip-to-chip communication operating up to 480Mbit/s. The DesignWare USB HSIC IP consists of integrated high speed digital and analog blocks, PLL, and I/O pads which are delivered as GDSII for advanced foundry processes. This can save designers significant time, cost and the risk of acquiring and integrating the IP separately. By eliminating the need for 3.3V signaling and 5V short protection logic, the DesignWare USB HSIC PHY offers up to 50 percent lower power and 75 percent smaller area compared to traditional USB 2.0 PHYs.

The DesignWare USB HSIC IP remains fully compatible with existing USB software stacks, allowing designers to lower system costs, shorten design time and improve productivity by reusing existing USB interfaces, drivers and firmware. The DesignWare USB HSIC digital controller, which is compliant with HSIC signaling, supports high speed USB 2.0 data transfers up to 480Mbit/s. The USB HSIC IP solution is ideal for applications such as 3G/4G handsets, smart phones, STBs and mobile internet devices.

"This solution enables manufacturers to integrate USB IP into mobile applications for higher bandwidth chip-to-chip connectivity with enhanced battery life and ultimately pass the cost savings to their customers," said Jeff Ravencraft, USB-IF president.

The first DesignWare USB IP for the new USB 2.0 LPM and HSIC standards is scheduled to be available in Q2. The new products will complement the existing DesignWare USB 2.0 family of digital controllers, PHY and verification IP.

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