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IMEC debuts mobile SDR baseband processor platform

Posted: 14 Feb 2008 ?? ?Print Version ?Bookmark and Share

Keywords:baseband platform? 802.11n? 802.16e? mobile TV?

A chip-level baseband platform capable of supporting 802.11n, 802.16e, mobile TV and 3GPP-LTE communication standards has been taped out by the European research consortium IMEC.

The SoC delivers in excess of 100Mbit/s throughput and is designed to serve as a flexible-air-interface (FLAI) baseband platform for software-defined radios (SDRs). The platform and its patented components and programming environment will be licensed to industry for commercial product development as white-box intellectual property (IP).

IMEC also expects to combine its FLAI platform and flexible radio front-end (SCALDIO) in order to demonstrate a fully operational SDR later this year.

Despite the chip's speed, a patented platform control and power management approach means the SoC consumes only a few milliwatts in standby mode. It is capable of receiving an immediate burst from any supported wireless standard (reactive radio).

When transmitting or receiving data bursts with multi-antenna encoding at more than 100Mbit/s, platform peak power is only 300mW.

IMEC released the news during the World Mobile Congress. It follows by about a week a number of releases at ISSCC relevant to wireless communications including IMEC unveils 60GHz multiple antenna receiver.

The FLAI platform incorporates: two IMEC-proprietary ADRES (architecture for dynamically reconfigurable embedded systems) baseband processors fully supported by a proprietary C-code compiler; three digital front-end tiles with a proprietary ASIP to assure sync-detection; an ARM9 processor and optimized AMBA interconnect to link the SoC's modules with on-chip memories.

The IP blocks come with reference platform control software and reference firmware for IEEE802.11n, 802.16e and 3GPP-LTE, as well as integration support.

FLAI specifications are as follows: 38mm? die area, four power domains, eight clocks, 270 I/O pins, 6.7Mbit memory (121 instances) and two FLAI-ADRES processors.

Each Flai-ADRES processor includes: 33 memory macro at 400MHz, 32Kbyte instruction cache, 128-entries config mem, 64Kbyte data scratchpad, 128Kbyte IMEM at 200MHz, 400MHz WCC clock rate and 25.6 GOPS.

- Jack Shandle
Wireless Net DesignLine

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