Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Interface

Overcome critical SoC architectural challenges

Posted: 18 Feb 2008 ?? ?Print Version ?Bookmark and Share

Keywords:SoC architectural challenges? consumer system challenges? tape-out?

By Tom De Schutter
CoWare Inc.

Jeff Haight
Sonics Inc.

Efficient design of complex, multimedia-intensive, heterogeneous multiprocessing SoCs for HDTVs and related CE systems presents daunting challenges. A collaborative effort among IC designers using CoWare's ESL tools and Sonics' SMX smart-interconnect IP designed for this class of SoCs enabled rapid optimization and verification of design aspects necessary to meet critical architectural challenges.

Difficulties with timing closure are frequently encountered, requiring tedious critical-path analyses and modifications to the logic, often requiring re-simulation and re-verification efforts before final tape-out. However, with the existence of a robust, high-level model, these efforts may be simplified. Making changes at a much higher level of abstraction (such as at the SystemC transaction level) helps speed the task of resimulating and reverifying by a couple orders of magnitude, allowing a great level of confidence in changes at the RTL that are to be quickly resynthesized.

Creating a complete high-level model provides advantages as well. During conversion to the next process technology node, the high-level model would remain the same. If cores are to be added, deleted or exchanged, only those directly affected would have their high-level models altered within the total simulation. Software development could continue and would precede the arrival of any new silicon. Verification suites could be quickly rerun, often including those required to meet industry and trade standards for audio or video streams, and their associated transport delivery specifications.

Mature interface
Interconnect IP have matured and are usually bundled with test and verification suites, and standardized interface. Interface generators and standards have matured as well, and ARM-Centric AHB interfaced-IP (or IBM's older PowerPC-centric CoreConnect) now see that increasing migration to the more sophisticated, feature-rich Open Core Protocol (OCP) standard. Bridges and gaskets to legacy protocols are increasingly available, providing a simple bidirectional path from A to B or I(nitiators) to T(argets).

Building onand active inthe evolving OCP capabilities, Sonics has developed a suite of interconnect IPs that include the ability to select a broad range of attributes for automated insertion into the fabric by choosing values in parameter sheets. These values include allowing multiple approaches to assigning different QoS levels to the different threads; instantiation of crossbars or shared links for connection to the various cores; enabling of sophisticated power management scenarios for dynamic voltage; and clock gating of different portions of the circuitry. They include other features as well.

Note that both the RTL and the SystemC are generated from the same database, ensuring a high level of congruence.

When dealing with any perceptual codecs at present (whether audio or video), there is no generally accepted quantitative engineering metrics corresponding to subjective quality. Many speech, audio and video algorithms require certain bit equivalence tests and artifact quantification thresholds to meet standards, but subjective analyses by an array of "experts" are still usually required. Unfortunately, pushing large volumes of video streams through complex RTL structures can require a lot of time that acceptable quality levels may be reduced to academic piffle in terms of market share. By raising the level of abstraction, video may be able to process orders of magnitude faster, and design choices can be verified as acceptable (or not) in a time frame that carries with it significant economic value.

A back-end video processor platform can be created in Platform Architect. Using the integration flow between Sonics StudioC and CoWare Platform Architect, different architecture settings can be simulated. The optimum architecture can be found by comparing the different analysis results:

  • In an SMX-shared link, all traffic shares the common interconnect resource. This interconnect topology results in the least amount of hardware, but causes contention whenever multiple initiators are trying to communicate with any one target. This particular interconnect architecture takes about 7ms to complete all the data traffic.

  • In an SMX-shared link with split transactions, the traffic still shares the common interconnect resource, but separate resources are provided for request and response, allowing for multiple outstanding transactions. This optimization decreases the amount of simulated time it takes to complete all the data traffic to about 2ms. Additional logic is required to handle the separate resources and to perform bookkeeping of the outstanding transactions, but the performance increase unequivocally justifies this.

  • In an SMX crossbar link, the interconnect topology provides parallel initiator-target communication for different initiator-target sets. So long as initiators are not communicating with the same target, there is no contention. The trade-off amount of logic vs. performance will have to be made based on the application constraints specified in the requirements document. The data traffic completes in about 5.2ms.

  • In an SMX crossbar link with split transactions, the interconnect architecture combines both optimizations, resulting in a dramatic performance increase over the first architecture. The data traffic completes in about 1.1ms.

This methodology can be applied to optimize the different aspects of the architecture, where the interconnect and memory subsystem need to be fine-tuned to reach the required specifications while avoiding overdesign.

The possibilities provided by many variables over many nodes make global optimization quite a challenge, even with well-designed IP implementations and concomitant user-friendly interfaces to ESL tools in the mix. However, as bidirectional information flow between tools at different levels of abstraction becomes more easily tracked, interpreted, modified, analyzed and responded to, greater choice in the granularity of optimization should become available.

About the authors
Tom De Schutter
is marketing manager of IP models and third-party relationships at CoWare Inc. Jeff Haight is director of technical marketing at Sonics Inc.

Article Comments - Overcome critical SoC architectural ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top