Intel, Microsoft pool funds for parallel programming effort

Intel Corp. and Microsoft Corp. will fund a new Parallel Computing Lab at the University of California at Berkeley in an effort to help define a parallel programming model that will serve the multicore computer processors already on the drawing board.

As many as 20 universities including MIT, Stanford and the University of Illinois, competed for the funding. The companies have not released details of the deal but according to one source, the grant is for about $2 million a year over five years. About 14 faculty members will work in the new Berkeley lab that quietly started operation on Jan. 21.

The grant is a sign of how the computer industry is shifting into high gear to help software catch up with advances in microprocessor design.

Both Advanced Micro Devices Inc. and Intel have said they will ship processors using a mix of x86 and graphics cores as early as next year, with core counts quickly rising to eight or more per chip. But software developers are still stuck with a mainly serial programming model that cannot easily take advantage of the new hardware.

"The industry is in a little bit of a panic about how to program multicore processors, especially heterogeneous ones," said Chuck Moore, a senior fellow at AMD trying to rally support for work in the area. "To make effective use of multicore hardware today you need a PhD in computer science. That can't continue if we want to enable heterogeneous CPUs," he said.

Parallel program
The Berkeley lab got its start in February 2005 with a series of weekly talks on the issue. In December 2006, researchers published a white paper detailing thoughts from those discussions.

A team of researchers has already started prototyping software systems based on ideas the group has fleshed out. They could publish preliminary results in a matter of months.

Essentially, the lab is aiming to define a way to compose parallel programs based on flexible sets of standard modules in a way similar to how serial programs are written today. The challenge in the parallel world is finding a dynamic and flexible approach to schedule parallel tasks from these modules across available hardware in complex heterogeneous multicore CPUs.

The group believes developers could create a set of perhaps a dozen frameworks that understand the intricacies of the hardware. The frameworks could be used to write modules that handle specific tasks such as solving a matrix. New run time environments could dynamically schedule the modules across available cores of various types.

The new approach would replace the global schedulers used in today's serial software. The frameworks would replace today's parallel libraries which are not always well suited to the specifics of a given parallel application and cannot be easily mixed and matched as needed.

Ongoing research
The Berkeley effort has set its sights on a long-term horizon beyond the 8-16 core processors likely to hit the market in mainstream CPUs in the next two to five years. Instead it will focus on problems programming chips with dozens of cores.

Researchers believe that over the next five years or so chipmakers will use a fairly diverse set of cores. However, as time goes on those cores may become increasingly similar to make it easier both to verify the silicon and program the hardware.

Researchers at Stanford are continuing to work in this area despite not getting the Intel/Microsoft funding. Their current focus is on combining two projects.

One project uses transactional memory technology to find ways to handle dynamic scheduling. Another uses a novel language called Sequoia aimed at data-intensive applications such as digital media processing.

Researchers at the University of Illinois, meanwhile, have explored ways to extract parallelism from today's serial code. They have also worked on compilers and programming models for next-generation graphics chips as well as the Intel Itanium processor.

- Rick Merritt
EE Times