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Watch out for India, Synopsys exec notes

Posted: 25 Feb 2008 ?? ?Print Version ?Bookmark and Share

Keywords:India? capacity design? Synopsys president?

When it comes to design capacity and capability, India is a powder keg about to explode. This is the observation of Chi Foon Chan, president and chief operating officer of Synopsys Inc.

India's future success will be determined by the types of design work performed. "About 32 percent of Indian engineers are working on 65nm design compared to 30 percent worldwide," Chan said during the India Semiconductor Association summit last week in Bengaluru.

India was marginally higher at 10 percent of its engineers working on 45nm design projects compared to 9 percent worldwide.

Measured in terms of maximum number of gates, Indian designers stood at 24 percent between 100,000 and 500,000 gates compared to 18 percent worldwide. It recorded only 9 percent at the 2 million- to 5 million-gate category. "It was 12 percent worldwide, but that's because these very high-end designs are concentrated in Silicon Valley," Chan said.

When compared to China, which still does a majority of its design work at 180nm and 130nm, India was far ahead on the design curve, he said.

Despite advanced design work, India remains a small player in the global chip industry. "India needs a strong industry-academy link, government programs as well as a strong manufacturing setup to become a major player in the semiconductor world," Chan said.

For example, Taiwan has a national SoC program; South Korea has an advanced IT strategy; and China had carefully drafted a national chip plan which has been incubating companies since 2002, resulting in over 450 fabs.

"The success of an ecosystem is built on the three fundamental props of having a talent pool, industry-academic cooperation and government support," Chan said.

- Sufia Tippu
EE Times

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