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More groups push standards for virtual prototyping

Posted: 10 Mar 2008 ?? ?Print Version ?Bookmark and Share

Keywords:virtual prototyping? SystemC? microprocessor? multicore?

New players are expected to push forward efforts to create standards for virtual prototyping as the next wave in system and software development, to allow tools and simulation models from various suppliers work together.

At the Mar. 10-14 DATE conference in Munich, the Open Core Protocol International Partnership (OCP-IP) will announce a new standard interface for a virtual prototyping debugger. The following week Eclipse Foundation is expected to kick off a new virtual prototyping effort.

In April, the group that oversees open power microprocessor cores is set to officially launch a standards effort in virtual prototyping. It aims to set guidelines for modeling interoperability and hybrid simulation models as well as establish a portal for interoperable tools and models for power cores.

Recently, Imperas Ltd made available as open source code an estimated $4 million of its processor models, APIs and a reference simulator. The technologies are part of yet-to-be released tools it claims take a higher-level view of systems prototyping aimed at software developers.

Collaboration is key
Virtual platform prototyping is a method that creates system-level simulators in software while engineers are still finishing the design of the underlying hardware. The approach allows software and hardware designers to work in parallel, speeding time-to-market. The new method is also a boon to chip designers, especially as their devices increasingly become systems-on-chips.

"The explosion in software needed to run multicore chips is stretching out time to market and straining customer relationships for chip makers," said John Barber, a research director at market watcher Gartner.

Virtual prototyping tools can help condense to three or four months the 12-14 months customers used to wait to get their hands on a new design. "It's a tremendous advantage," said Barber.

But prototyping tools still do not accurately spit out gate-level chip designs nor do they have all the standards in place to make sure models and tools interoperate.

"There's still a lot of work to be done and I do not expect these standards to become mature in the next six to 12 months," Barber added. "But if they don't mature, this will remain a cottage industry," he said.

"I think what companies are starting to realize is that this game is about putting together bits of intellectual property from different places, and that no one can do it all from scratch," said Mark Burton, founder of the GreenSocs open source effort and an active member of virtual prototyping standards work in three other groups.

"You need to integrate [various] component models into a virtual system prototype, so things need to plug and play together," Burton added.

Eye on SystemC
Burton and others see the core of that work coming from users of the SystemC language. The Open SystemC Initiative (OSCI) has set standards for the systems-design language and the OCP-IP group has been developing a range of so-called Transaction Level Modeling standards for it, the latest a debug standard coming out at DATE.

"Some models exist in one or another language, but SystemC is the glue that can hold them together," said Burton.

The OSCI and OCP-IP "are the two most important efforts and Vast is very much supporting them," said Jeff Roane, VP of marketing for Vast Systems a provider of virtual prototyping tools.

"Every customer we engage with is developing peripheral models in SystemC and the models are getting standardized so we are moving toward a plug-and-play world," Roane added.

For its part, the Eclipse is expected to announce at the EclipseCon later this month a new effort to tie the SystemC work to its standards for tool user interfaces. "Our latest release added support for Eclipse," said Roane of Vast.

Separately, the Spirit Consortium is defining XML standards for chip-level models, and the GreenSocs group is providing a home for open-source efforts.

"We are not Spirit compliant but we are XML based, and as for GreenSocs, we haven't seen a lot of customer demand for their work yet," said Roane. "There's no shortage of standards efforts, but at the end of the day only a few of them get adopted by a broad community," he added.

It's unclear whether new efforts at systems modeling may emerge around other hardware design languages such as Matlab, Verilog and VHDL. "It will be interesting to see if other consortiums emerge," said Barber of Gartner.

Simon Davidmann, president and CEO of Imperas, said the SystemC work tends to focus on low level needs of hardware developers while his company will release as early as the Multicore Expo in April higher level tools aimed at the needs of software developers.

"SystemC is too complex, low level and expensive for many software developers with models that can cost hundreds of thousands of dollars," said Davidmann. "We are aiming at the next level of abstraction up and no one is developing tools at this higher level," he added.

The Imperas tools will give software developers an ability to verify, debug and analyze code without needing to know details of the underlying hardware such as bus structures. It will also allow users to model interactions of distributed systems on an Ethernet network, Davidmann said.

Roane of Vast had no comment on the Imperas move to make some of its technology open source. "They haven't said a lot about what they are doing so it's difficult to comment on them," Roane said.

Power core focus
Meanwhile the group is ramping up an effort centered on Power cores.

"Advances in simulation technology promise to fulfill the industry's need for a fundamental new approach to software development that can optimize increasingly complex electronic system designs, meet ever-shorter development cycles and deliver time-to-market advantages," said Kaveh Massoudian, a program director in IBM's systems and technology group and technical chair for the virtual platforms work group at

"However, there needs to be interoperability and flexibility among various levels of abstraction and offerings from different vendors, and is leading an effort to integrate the various standards bodies' efforts for the benefit of all [Power] customers," Massoudian added.

The work group includes members from AMCC, Freescale, IBM, Synopsys, Vast and Virtutech. It expects to start technical work shortly.

"We develop models for our cores within IBM, but for the design process to be effective we need to get these models into the proprietary tools of companies such as Vast and others," said Michael Paczan, chief technology officer of and a former lead Power PC designer at IBM. "That's where we need interface standards," he said in a recent panel discussion hoisted by Vast.

- Rick Merritt
EE Times

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