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Bring DFM/DFY into the routing engine

Posted: 17 Mar 2008 ?? ?Print Version ?Bookmark and Share

Keywords:DFM/DFY tools? manufacturing and yield? rules-based model-based technique?

In the context of digital ICs, design-for-manufacturing (DFM) refers to a variety of techniques used during the process of implementing the design to ensure that it can be manufactured correctly. Meanwhile, design-for-yield (DFY) refers to any technique used to improve the yield of a particular device. In reality, these techniques are very much intertwined that it is becoming common to consider them as one entity: DFM/DFY.

Yield is a function of the device's manufacturability and there are three main "buckets" into which yield-related problems may be categorized. These buckets are commonly referred to as random (sometimes called statistical) yield, systematic yield and parametric yield:

Random yield!This form of yield is a function of random effects that occur during the manufacturing process. For example, no matter how clean the wafer manufacturing environment is, there are always some small particles in the atmosphere that may land on the surface of the chip.

Such particles may cause catastrophic faults in the form of open or short circuits. Alternatively, in some cases they may cause parametric variations. For example, a particle may land on a non-critical area of a particular layer and may cause a non-planar feature (bump) in subsequent layers. In turn, this bump may end up varying the width or thickness of a wire on a higher layer, changing the electrical characteristics of that wire and resulting in a parametric yield failure.

Systematic yield!This refers to a class of manufacturability issues that are the result of some combination and interactions of events. These issues can be identified and addressed in a systematic way.

Many systematic yield issues are design-dependent. For example, some designs may have high densities (concentrations) of wires in certain areas and low densities in others. Such density variations can affect the amount of etching that takes place in the various regions. Similarly, in the case of process steps like chemical-mechanical polishing (CMP), variations in wire density can cause differences in the effectiveness of the polishing process, which can result in areas where some wires are thinner than others. In turn, this affects the resistance and capacitance values associated with these wires, which can modify the power and performance (timing) of the design.

By understanding systematic effects during the design implementation process it is also possible to create a design in such a way as to minimize their effects on yield.

Parametric yield!It refers to the fact that a chip may perform its logical function correctly ("stimulus X returns response Y"), but variations in the device's parameters may mean that it does not achieve its specified performance goals. If transistor channels aren't formed quite as expected, for example, the result may be lower drive capabilities, increased leakage current, greater power consumption, increased resistance and capacitance (RC) time constants, and slower chips.

Alternatively, issues in the etching and CMP processes may cause non-planarity on the surface of the chip. This can cause wires to have higher resistances and/or capacitances than expected, which will result in the device's speed falling and its power consumption rising.

An aspect of parametric yield that is becoming extremely significant is variation or variability. There has always been an issue regarding inter-wafer variation, which refers to slight differences between wafers in a lot. In today's technology nodes, there can be significant variations between different areas on the same wafer (intra-wafer variation) and even on the same die (on-chip variance).

By understanding parametric effects during the design implementation process, it is possible to create designs that minimize loss in chip performance and yield. If DFM/DFY issues are not addressed, it may simply not be possible to achieve economically viable yields in the forthcoming technology nodes.

Bountiful yield
A variety of techniques are currently employed to increase manufacturability and yield. These approaches are generally considered to be rule- or model-based.

Rule-based techniques!The first DFM/DFY tools were rules-based. The term "design rules" refers to a collection of rules that must be met by the physical design engineers and their tools. Examples of these rules would be the minimum width of wires and the minimum spacing between wires. One problem is that the number of such rules is increasing dramatically with each new technology node. In the case of the 180nm node, for example, there were typically only a few dozen such rules, while today's 65nm node can have several thousand rules.

Figure 2: Traditional vs. new DFM/DFY-aware flow: The solution is to bring DFM/DFY upstream into the design process to create a design that is correct by construction.

In many cases, the rules are very restrictive that the result is to guard-band the design, leaving a significant amount of performance on the table. In some cases, the design ends up being very guard-banded that it is impossible to achieve its original performance goals. Even worse, the complex relationships between different manufacturability and yield mechanisms mean that it's not possible to formulate an appropriate rule that would be meaningful to the design tool.

Model-based techniques!DFM/DFY applications have started to apply model-based techniques. This may include modeling the way in which light will pass through the photomasks and any lenses; how it will react with the chemicals on the surface of the silicon chip; and how the resulting structures will be created.

Best of both worlds
In reality, DFM/DFY tools need to use a mixture of rules- and model-based techniques as appropriate. Using model-based techniques for certain tasks allows the number of rules to be reduced and the remaining rules to be simplified, while attaining higher quality in the final chip layout.

The solution is to bring DFM/DFY upstream into the design process; to create a design that is correct by construction; and to hand-off a design that is as manufacturing- and yield-friendly as possible. The obvious candidate to subsume DFM/DFY analysis and implementation is the routing engine, the "front door" into the manufacturing process. For ASICs, routing currently accounts for approximately 60 percent of design delays.

- Mitch Heins
VP of Business Development, Pyxis Technology Inc.




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