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Synopsys, SMIC tip 90nm reference design flow

Posted: 18 Mar 2008 ?? ?Print Version ?Bookmark and Share

Keywords:design-for-test? RTL-to-GDSII design flow? 65nm?

Synopsys Inc. and Semiconductor Manufacturing International Corp. (SMIC) have released an enhanced 90nm hierarchical, multivoltage RTL-to-GDSII reference design flow that benefits from advanced synthesis, design-for-test (DFT) and DFM capabilities. Key features of the reference flow include topographical synthesis in the Design Compiler Ultra product, scan compression in the DFT MAX product and DFM features in the IC Compiler place-and-route product. Together these capabilities help to lower the cost of implementing and testing SoCs.

"We have worked closely with Synopsys to enhance our 90nm reference flow. The latest iteration builds upon the previous flow's low power consumption, DFT and DFM capabilities," said Paul Ouyang, senior fellow of marketing and sales at SMIC. "The new flow reduces synthesis iterations and lowers test costs, providing our customers a path to significant cost savings and lower design risk."

The enhanced reference design flow 3.2, based on SMIC's 90nm low-leakage process and Synopsys' Pilot Design Environment, has been validated on Synopsys' Galaxy Design Platform with the ARM low power design kit developed for SMIC's 90nm process. The reference flow uses Design Compiler Ultra topographical technology to accurately predict post-layout timing, power and area during synthesis, thereby reducing costly design iterations between synthesis and layout.

Advanced capabilities for low power design include insertion and placement optimization of isolation cells, creation of multiple voltage areas and power meshes, and synthesis of multiple voltage-aware clock trees. To help reduce standby leakage, the design flow uses power-gating techniques that shut off areas of the chip when they are not needed for a function. DFT MAX synthesizes scan compression circuits that substantially lower costs by decreasing the amount of data and time required for manufacturing test. The tool reduces the number of scan chain connections that cross voltage domains, lowering the area impact of DFT by reducing the number of required level shifters and isolation cells. Other DFM capabilities in the flow include via optimization and wire spreading and antenna fixing with Hercules runset.

Reference Design Flow 3.2 is already available.

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