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FPGAs/PLDs??

Multiply efficiently in wireless base stations

Posted: 01 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? WiMAX system design? OFDM? multipliers? digital upconversion?

Emerging broadband wireless protocols based on WiMAX and its derivatives demand an increasing amount of throughput and data-rate. Fast chip-rate and digital RF processing by these protocols are optimally implemented in hardware using FPGA solutions.

FPGAs are ideal as a high-performance, cost-effective solution to implementing the digital functionality of these physical layer protocols because of four resources. FPGAs have DSP blocks to implement the multiplier and adder/accumulator functions required for various FIR filtering and FFT/inverse FFT operations. They also have Serdes transceivers to support the Common Public Radio Interface (CPRI) and Open Base Station Architecture Initiative (OBSAI) interfaces between radio heads and baseband digital boards. FPGA tout significant embedded block memory (EBR) to store filter coefficients, perform block interleaving and implement FEC decoding (Turbo, Viterbi, Reed-Solomon, etc.). And they feature high-speed LVDS I/Os to support wide parallel interfaces to and from DACs and ADCs. The converters define the boundary between RF/analog functions and less expensive digital baseband logic. Higher rates of this interface allow more integration of digital upconversion (DUC) and digital downconversion (DDC) functions into the low-cost FPGA solution.

This article focuses on the first resource, DSP multiplier blocks. Through reduction and optimal implementation of DSP multiplier blocks in FFT and FIR implementation, the designer is able to minimize resources while meeting throughput requirements. This allows users to migrate to the most cost-effective FPGA devices available.

View the PDF document for more information.





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