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Reduce EMI with proper SI design

Posted: 01 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:PCB? signal integrity? high-speed design?

Today's PCB designers are faced with the competing challenges of smaller, higher-density applications coupled with high frequency and high-speed signaling. A multitude of standards now exists that utilize high-speed serial signaling such as HDMI, PCIe, SATA, and DDR memory. The higher speeds give rise to greater demands on PCB designs to meet power signal integrity (SI), power integrity (PI) and EMI specifications. The challenge becomes especially acute for low-cost commercial devices where traditional SI design rules may be ignored or "traded" in exchange for a board with fewer power and ground planes or a higher density design with less than optimum signal routing.

SI, PI and EMI design used to be considered separate disciplines, each with its own design rules, analysis methods, and measurement techniques. A more modern approach is to recognize that there is a strong interdependence among the three, and that optimum board design requires an integrated approach. A SI problem, for example, may lead directly to an EMI problem. This article provides a summary of the important design considerations and presents an LVDS case study for integrated SI, PI and EMI design.

Reducing EMI/EMC problems early in the design cycle using a virtual design process has been a dream for many engineers fettered with the problem of fixing complex coupling issues on nearly finalized designs. However, the complexity of designs and an under-appreciation for the power of today's tools has limited the widespread adoption of simulation in this area.

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