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Source-level Codelink supports multicore debug

Posted: 04 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:source-level debug? Questa Codelink? embedded processors?

An integrated, source-level debug environment targeting processor driven tests has been launched by Mentor Graphics Corp. as an expansion of its Questa Functional Verification Platform. The Questa Codelink is designed to speed the validation of ASICs containing one or more embedded processors.

Use of sign-off accurate, RTL processor models to drive cycles into multicore SoC designs is a common practice among hardware verification engineers. This method of test is identical to the SoC's actual operation and provides highly effective functional verification. A major limitation to this approach is the lack of an effective debug environment. Isolating the cause of a failing processor driven test is a tedious and time-consuming process as RTL processor models delivered by the core vendor provide little or no debug visibility.

To advance the use of processor driven test, Mentor developed Questa Codelink, a rich source-level debugger for RTL processor models supplied by ARM and MIPS. Codelink employs patent-pending technology, which shadows the RTL model and generates a rich debug dataset. By presenting the user with a full view of software variables, call stack, registers, and memory, test failures can be isolated in minutes rather than days or weeks.

Multicore debug
With one third of all SoC designs moving to multicore in the next two years, it is important that Codelink support multicore debug. Tracking multiple code threads and observing message passing via shared memory are key elements in debugging synchronization failures in multicore systems. Codelink offers a variety of techniques for efficiently organizing and viewing the many representations of relevant data associated with multicore source-level debug.

In addition, Codelink has the ability to log batch runs and debug interactively post-simulation, eliminating the need to rerun long simulations in order to debug them. Codelink replays a 15 hour simulation in 3 seconds, yielding highly interactive debug of large simulations. Codelink also supports stepping backwards through source or assembly while variables, memory, and registers views accurately reflect the state of the system.

"Over the past year our teaching customers like InterDigital Inc., have been instrumental in helping us to refine and enhance the Codelink product," said Serge Leef, general manager of Mentor's system level engineering division. "What has emerged is a highly efficient debug environment for MIPS and ARM based SoCs."

"Codelink has proven to be a highly cost-effective and efficient tool for us, particularly the replay feature," said Kenneth Bartsch, verification lead at InterDigital. "Prior to Codelink, certain bugs required multiple one-day re-simulations to fully diagnose. With Codelink replay we simulate just one time, and isolate the failure (hardware or software) immediately. Both software and hardware engineers like the tool. Codelink was key to us taping out our new SlimChip SoC on schedule."

The Questa Codelink product is available now with a starting price of $28,400. The following families of processors are currently supported: ARM7, ARM9, ARM11, ARM Cortex, MIPS 4, MIPS 24 and MIPS 74.





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