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Capturing and sharing IP in PCB design

Posted: 14 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:electronic system design flows? sharing IP cores? PCB design?

By Dean Wiltshire
Mentor Graphics Corp.

This article discusses the disconnect between the digital design engineer's vision of bus structures on the PCB and the failure of tools to capture and route this vision in an efficient manner.

Worldwide, there are different electronic system design flows and roles. This article assumes a design flow that may or may not match the flow and roles of your organization, yet the solutions discussed fit into any flow. The first part of this two-part article follows the capture of intellectual property (IP), by the design engineer and collaboration of this IP throughout the remaining design flow. The second part of this article focuses on the PCB designer collaboration of the IP through the remaining design flow.

While designing and capturing the logic, the design engineer has envisioned the bus structure and its relationship among the components. This envisioned structure is considered IP, typically a valuable asset to their organization. The problem is capturing and sharing this IP.

Often, design engineers attempt to capture and communicate IP in a hand drawn document or on a paper napkin. While many aspects of EDA are in fact automated, this process has not had effective tool support. A hand drawing on a napkin has been the most efficient to date (Figure 1).

Figure 1: The napkin shows an example of a typical Engineering sketch of a bus structure.

While quick to capture, the napkin may or may not physically map to the PCB. This is a problem because of size issues, such as width of the physical bus, mechanical parameters of the card, physical size and pin outs of components. Thus, the original IP may be completely invalid because it is physically impossible to follow; EDA tools must not only replace, but also improve upon the napkin. They must effectively capture the IP and communicate accurate, usable/reusable IP throughout the design process.

When the IP is accurately captured, collaboration is required throughout the remaining design flow. Effective collaboration shortens the design timeframe by preventing the re-entry of IP by others. Additionally, by using the exact IP, the original intent is maintained. Errors and misunderstandings are removed with effective collaboration with the results being increased efficiency in the design flow.

Topology planning
What is needed is a topology planning tool. This tool should allow the design engineer to define and capture the bus structure and effectively communicate it throughout the design flow. To effectively plan bus structures, they first must be logically defined. Bus definitions can come forward from captured logic in the schematic or ASCII input, depending on the design flow. With buses defined, a card outline, components and board stackup, the design is ready for accurate capture of the topology.

Figure 2: The "P" in the bus path represents a packed bus, meaning; the routed traces are as compressed as possible and follow these paths, on the specified layers.

The tools to capture topology must be easy to use, flexible and accurate while providing useful visual feedback. This should start with a true, exact physical representation of bus paths. A 64-bit bus must truly represent the width of 64 parallel traces and 63 trace-to-trace clearances, all while understanding impedance implications per layer. Also, as buses are drawn on different layers, they need to be visually represented on these layers. The purpose of all this is to ensure what the design engineer is capturing actually fits into the sections of the PCB where they're intended to, otherwise the integrity of the IP is in jeopardy (Figure 2).

Design engineers must have flexibility when creating their IP and they should be able to draw their bus paths with a few key components placed, all components placed or no components placed. A topology planning tool should aid in the creation process by providing flexibility, not force a procedure.


Figure 3: U1002 is being placed from bus PCI2. Note the netlines render to a PCI2 bus path and component pins.
Click to view image.

Since the placement of components affects the bus structure and vice versa, efficient topology planning must support the placement of components by buses. During placement, designers should be able to filter and place those components that share a bus. As illustrated in Figure 3, the selection of a bus should filter the component list to include components associated to the selected bus.

Typically, when placing components, net lines span between component pins and aid in placing (Figure 4a). This provides a useful purpose, real-time feedback of component connections to associated components. Yet, as more components are placed, more net lines are brought into the display. For complex designs, the density, overlapping and twisting of net lines can cause more confusion than guidance.

From Figure 4, both displays are useful while capturing IP. Yet the evolved image in figure 4b shows the organization and visual benefit brought through topology planning. Net lines are bundled in their layer specific paths, showing accurate space requirements. The results are a clear representation of bus to component relationships while understanding scale.

As they draw their bus paths, design engineers create order in the placement and are able to visually see and dictate how the bus is routed and components placed.

Bus paths may accommodate any count of bits up to the total defined in the bus. This provides great flexibility in planning the bus structures. For example, while drawing a 64-bit bus the decision was made to split it into two 32-bit paths and put them on different layers. At any point, these bus paths can be merged into a larger bus path, or further reduced to smaller bit count buses.

To continue the example, one of the 32bit bus paths was split into two 16bit paths as shown in Figure 6. This was done to efficiently connect to a Ball Grid Array (BGA) component package shown in the upper left hand side of Figure 5.

Topology planning must include optional abilities to capture complex bus structures to include:

  • Layer changes with via patterns

  • T-Junctions

  • V and T splits

  • Netlines spanning from the sides of bus paths

  • Overlapping paths of same bus

  • Netline assignments with bit ordering


Figure 4: The two parts of the figure show a general flow of interconnects between components.
Click to view image.

While flexible, a "packed" bus structure does not work with all topology planning scenarios. If, for example, there are two BGAs close together and sharing a 64bit bus, there may not be enough room for a packed bus path. In this scenario it is better to go with an unpacked area for the bus. An unpacked area doesn't dictate a packed structure. Instead, it specifies layers, layer bias per selected layer and area for the selected bus bits to route. The design engineer is still capturing IP, yet with an area border, layers and layer bias.

Timing concerns
Timing concerns create signal delays that can consume vast amounts of trace space on a PCB. Rather than being surprised to where they'll fit, it's best to estimate the needed space and plan where tune delay lengths will be added.

A good topology planning tool provides this capability, where it's needed during the planning stageallowing the design engineer to specify areas on the PCB to locate the delay lengths. Planning ahead of the process ensures the needed space is available. Optionally, a plan should have the ability to manage and specify the area for signal delay traces.

Planning for signal integrity
With ever increasing signal frequencies, it is crucial to consider signal integrity during topology planning. Planning for signal integrity includes insuring against crosstalk, parallelism and planning for return signal path. Typical design flows find signal integrity problems after most traces are routed and the design almost complete.

Depending on the signal integrity problem, the solution may require space between signals traces, or a ground shield between the two signal traces or a ground/voltage plane clear of obstacles. Yet the PCB design is almost complete and may have high trace density in the area of the PCB where the problems are occurring. This is the wrong time in the design cycle to be informed of signal integrity problems because there may not be enough physical space to easily solve the problem.

Topology planning is the right time to plan for signal integrity; before traces are committed to the PCB. Rather than trying to find space after the interconnects are completed, it is better to plan for a return path, prevent crosstalk and parallelism before trace routing is started. Otherwise, the necessary space for a plane layer, spacer or ground shielding may be unavailable. If planned for, instead of reacting to signal integrity issues, the design cycle is further shorten by anticipating these potential problems early and necessary signal performance is achieved.

Figure 6: You can split of a 32bit bus into two 16 bits bus paths. On the right you can see the topology routing results.

When IP is captured, it is time to share it through collaboration. Seamlessly, the design engineer captured IP should collaborate and drive the placement of remaining component and routing of traces. The second part of this two part article will discuss the PCB designer role and usage of topology planning and topology trace routing.

About the Author
Dean Wiltshire
is a product architect in the system design division of Mentor Graphics.

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