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Scale voltage to manage power consumption

Posted: 16 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:voltage-scaling techniques? DSP? static dynamic power consumption?

The semiconductor industry's eternal mantra "smaller is better" is running into trouble with power issues as feature sizes continue to shrink. CMOS process technology is the dominant approach for modern microprocessor and DSP products. As CMOS process technologies migrate from 90nm to 65nm and below and as chip densities increase, static and dynamic power consumption often rise above acceptable levels. Apply voltage-scaling techniques to manage both.

Following Moore's Law, chip-level transistor densities and chip complexity double about every 24 months and IC performance increases proportionally. There's greater integration for more functionality in the same or less area, additional features and higher speeds at lower cost.

DSPs have enabled a slew of new multimedia applications such as portable media players, smart phones and rich imaging devices. At the same time, infrastructure applications in telecommunications, wireless communications and networking have benefited tremendously.

CMOS technology is commonly used for modern DSP and microprocessor designs. Compared with others, this technology is easier to process and scale. In addition, it offers a good performance-to-power-consumption ratio.

While scaling of advanced technologies enables more elements and functionality per area, the power-per-area (power density) also increases. As steady silicon technology development pushes CMOS below the 65nm process technology node to even smaller structure sizes, the issue of chip-level static and dynamic power takes on greater importance.

Static power
Static power consumption is power dissipated when the device is powered up but idle (i.e. there is no transistor switching activity). Thus, static power consumption is independent of workload and any usage scenario. The main component of static power consumption is leakage current IL, which is mostly affected by transistor type including physical dimensions (width and length) and various characteristics of the silicon fabrication process technology (e.g. oxide thickness and doping profile).

At the transistor level, the static power consumption PS is the product of the supply voltage Vss and IL. Contributors to leakage current are the sub-threshold leakage IL,ST while the transistor is switched off; the junction leakage IL,J; and the tunneling leakage IL,GT.

Dynamic power
On the other hand, dynamic power consumption is a function of the clock speed and the transistor's capacitive loading. It again depends on the physical transistor geometry.

With advanced process technology nodes, static power consumption is increasing faster than dynamic power consumption. As structure sizes decrease and as field strengths within the element generally go up, designers generally adjust the operating voltage to reduce the dynamic power consumption. However, the static power draw becomes more of a factor, increasing exponentially with leakage current. Moreover, the sub-threshold leakage current also increases exponentially with temperature.

The increase in static power consumption causes more concern, as it affects the total active die and power densities, and increases the risk for hot spots. Thus, managing both static and dynamic power consumption without adversely affecting performance requires a certain degree of intelligence and adaptability at both the chip and system level.

Intelligently adaptive
Static power consumption is also affected by the characteristics of a chip's fabrication process regardless of the type of transistor in the device. Thus, the logical place to begin managing static leakage currents is at the level of the silicon itself. As the silicon is processed, there is a natural and slight variation in its electrical characteristics across both a single wafer and entire wafer lots. This variation follows a density distribution that is a function of material and production parameters.

This variation is often referred to as the "strength" of the fabrication process and is said to vary from weak to strong. This characterization has no bearing on the quality of the chips produced; it is merely a way to describe the variables in the silicon production process.

Where a particular device falls on the silicon process scale, however, is a relative indicator of the electrical behavior and associated power consumption characteristics of that device. The semiconductor devices that fall on the strong end of the process scale sare able to achieve higher switching speeds, but have higher leakage currents. Conversely, devices that fall on the weak end of the silicon process scale have a lower maximum achievable speed, but they dissipate less power through leakage currents.

How can a designer benefit from knowledge of this phenomenon? One way is to scale the voltage according to the silicon's electrical characteristics. This method maximizes performance while minimizing the power consumption caused by leakage currents. The device can be tested during manufacturing to measure its electrical characteristics. The voltage can then be scaled to meet the chip's performance and power consumption requirements.

Consider a DSP chip made from silicon on the strong end of the process scale that can support slightly higher switching speeds than specified, but draws slightly higher leakage currents. If a power management device for that DSP is able to detect that device's specific characteristics, it can scale down the supply voltage to reduce power consumption without jeopardizing the chip's specified performance.

The TCI648x has an integrated thermal diode to take advantage of temperature-dependent dynamic voltage scaling.

The same logic could be applied to a DSP produced from weak silicon. The power management device can increase the voltage to ensure that the required performance level is met while power consumption stays within a specified range.

The research indicates that the most significant power savings can be achieved by adjusting the core voltage of devices that fall on the "strong" end of the silicon process technology scale.

Power savings
Voltage scaling can also be applied to reduce dynamic power consumption (i.e. the power consumed while the system is in operation). In this case, temperature can be used as the variable to drive changes in core voltages. For example, at high temperatures, the voltage to the device can be decreased, which further reduces power consumption.

Conversely, at low temperatures the core voltage of the device can be increased to accelerate performance while having a relatively low effect on power consumption. Device-related thermal information is needed to enable this type of power-saving function. TI's TCI648x DSPs provide an example of how this is implemented.

The TCI648x has an integrated thermal diode to take advantage of temperature-dependent dynamic voltage scaling. This diode and an external temperature sensor such as the TMP411 can sense the device's temperature and provide feedback to internal TCI648x logic. In this instance, the DSP is able to take advantage of both static and dynamic power savings.

The DSP creates a voltage code by combining the dynamic thermal information with device-specific embedded information on the strength or weakness of the silicon's process technology. This voltage code is presented to the system's power management device. In the case of the TCI648x, the power management device can scale the voltage of the power provided to the DSP over a range of 0.9-1.2V. Thus, with adequate attention, designers can minimize power consumption while keeping the benefits of Moore's Law basically intact.

- Heinrich Hillmayr
Business Development Manager
Texas Instruments Inc.





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