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Serial-output ADC needs fewer FPGA I/O pins

Posted: 16 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:serial interface? ADC? FPGA? I/O pins?

Linear Technology Corp. has announced a 16bit, 105MSps ADC that enables a simple, new benchmark for digital communication between high-speed ADCs and FPGAs. The LTC2274's new high-speed 2-wire serial interface reduces the number of data I/O lines required between a 16bit ADC and the FPGA from 16 CMOS or 32 LVDS parallel data lines to a single, self-clocking, differential pair communicating at 2.1Gbit/s, freeing up valuable FPGA pins.

Serial data communications offers simplified layout, and requires less board area for routing, while providing the flexibility to route across analog and digital boundaries. In noise-sensitive applications, the serial interface provides an effective isolation barrier between digital and analog circuitry and serves to eliminate coupling between the digital outputs and analog inputs to reduce digital feedback.

The LTC2274 output data is serialized according to the Jedec serial interface specification for data converters (JESD204) using 8b10b encoding, and is compatible with many FPGA high-speed interfaces including Xilinx's Rocket IO, Altera's Stratix II GX I/O and Lattice's ECP2M I/O. At 2.1Gbit/s, the LTC2274 promises the fastest serial interface of any ADC on the market. Applications such as communications equipment, multichannel systems, space-constrained designs and instrumentation could all benefit from the LTC2274's interface and feature set.

The LTC2274 offers several features to improve overall system design. For high-sensitivity receiver applications, the LTC2274 provides an internal transparent dither circuit that improves the ADC's SFDR response beyond 100dBc for low-level input signals. To avoid any interference from the serial digital outputs, an optional data scrambler is available to randomize the spectrum of the serial link. Serial test patterns are also incorporated to facilitate testing of the serial interface. While the LTC2274 may be operated at a maximum sampling rate of 105MSps, the internal PLL may be configured to lock at one of three different sample rate ranges. An on-chip clock duty cycle stabilizer circuit has been implemented to facilitate non-50 percent clock duty cycles. Separate shutdown pins for the analog and digital sections are provided to conserve power.

The LTC2274 maintains high-performance advantages, promising excellent SNR performance of 77.5dB and SFDR of 100dB at baseband. Ultralow jitter of 80fs RMS enables undersampling of input frequencies up to 500MHz with excellent noise performance. The LTC2274 consumes 1.3W from a 3.3V analog supply.

The LTC2274's serial output allows it to fit in a 6mm x 6mm QFN-40 package, less than half the size of similar 16bit ADCs with parallel outputs. In addition to the 16bit, 105MSps LTC2274, pin-compatible 80MSps and 65MSps versions will be releasing this summer. Production quantities of the LTC2274 will be available in July in both commercial and industrial temperature grades. The device is competitively priced at $68 each in 1,000-piece quantities.

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