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Production-ready processor core for FPGAs rolls

Posted: 21 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:processor? FPGA design? ReadyIP program?

Tensilica Inc. has announced that its Diamond Standard 106Micro processor core is now available for FPGA design as part of Synplicity's newly announced ReadyIP program. The company says it is the industry's smallest licensable 32bit processor core based on an industry-standard architecture.

The Diamond Standard processor cores from Tensilica are things of beauty to processor aficionados, butuntil nowwe've always thought of them in the context of SoC designs. Of course you could implement them in an FPGA as part of an ASIC/SoC prototyping activity, but they really weren't tailored/intended for an FPGA deployment, until now.

With no up-front licensing fee and no royalties until 10,000 units, the Diamond Standard 106Micro is essentially free for many FPGA designers. This 106Micro offering combines the benefits of the "free IP" that FPGA users expect to receive from their FPGA silicon vendor, with the freedom to migrate their design to other FPGA architectures, structured ASIC or standard cell implementations. Synplicity's ReadyIP program delivers an encrypted design methodology for FPGA implementation, allowing designers to incorporate the Diamond Standard 106Micro using the Synplify Pro and/or Synplify Premier synthesis environments. Additionally, Tensilica supports Synplicity's new System Designer IP integration tool by providing IP-XACT models of the processor. Also, a free 15 day evaluation version of the Xplorer Diamond Edition software toolkit and IDE is also available through the ReadyIP program and from Tensilica website.

Diamond details
Based on the Tensilica's Xtensa architecture, the Diamond Standard 106Micro CPU, is ideal for designers looking for a basic 32bit controller, particularly for those migrating up from an 8- or 16bit controller. Although the Diamond 106Micro is extremely small, it employs a 5-stage pipeline so it can easily achieve frequencies of >100MHz in many different FPGA fabrics. By modelessly switching between 24- and 16bit narrow instructions, it achieves a much higher code density than other 32/16bit architectures.

The Diamond 106Micro has an iterative, multi-cycle 32x32 multiplier that greatly enhances performance on arithmetic and DSP code. The processor uses a non-windowed 16-entry AR register file to keep area low. The tightly coupled instruction and data memory on the Diamond 106Micro can be used to store performance-sensitive code and data, for example, to achieve high performance on interrupt handlers.

The Diamond Standard 106Micro has a rich interrupt architecture with an integrated interrupt controller with 15 interrupts and an integrated timer. This simplifies system design since no external hardware needs to be added for these functions. The Diamond 106Micro includes an AHB-lite interface, so designers can easily integrate it into a design with existing AMBA-based peripherals.

Pricing and availability
The Diamond Standard 106Micro for use with Synplicity's Synplify Pro software for FPGAs is available now for download through the Synplicity tool. A click-through license explains the terms of use for FPGA designers. A complete software tool suite is available for a 15-day free evaluation from the Synplicity tools or Tensilica's website at www.tensilica.com.

- Clive Maxfield
Programmable Logic DesignLine





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