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SoC complexity, cost compel companies to collaborate

Posted: 21 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:SoC design? IP collaboration? cost and complexity?

Growing complexity and the staggering costs associated with designing SoCs are forcing companies to seek collaboration on a variety of intellectual property (IP) issues.

Chip industry executives and IP vendors speaking at an IP symposium in California this week agreed that greater collaboration is needed on issues like design reuse and standards.

The key drivers are complex designs that are gradually moving to 45nm feature sizes and skyrocketing costs associated with chip design and generating internal IP. Company engineers estimated the cost of some SoC designs has soared to $100 million per device.

"We need intense innovation in the IP industry [and] intense collaboration," said Gadi Singer, vice president of Intel Corp.'s SoC Enabling Group.

Chipmakers are coping with skyrocketing R&D costs by seeking more IP partners. At the same time, they want to expand their IP licensing business to recoup some of their R&D investment. But some experts said greater collaboration is stymied by the poor quality of some IP blocks and fragmented industry standards.

"Only a small number [of IP providers are] viable and have the deep pockets needed to provide quality," said Peter Hirt, manager of IP procurement and partnerships at STMicroelectronics. Maintaining quality is a challenge, and the quality of IP providers "is not there beyond the top tier of companies," Hirt said.

Hirt added that one way aspiring IP providers can improve quality is to "bundle up" with a verification specialist.

A likely first step in increasing collaboration on IP development for SoCs will be standards efforts. Panelists said the move to consolidate many standards initiatives under the IEEE will help since many affecting SoC design are fragmented.

Standards and collaboration will be a big part of this," said Victor Berman, president and CEO of IP vendor Improv Systems Inc. Berman added, however, that design reuse is "hog-tied" by inadequate methodology standards.

Moreover, Berman said, "emerging markets [like China] are not in the loop" for standards setting and "global standards are chaotic."

Meanwhile, as the amount of internal and licensed IP is integrated into new SoC designs, companies are increasingly nervous about legal issues such as the assertion of IP rights by smaller companies and legal liability associated with product recalls. The growing use of "system-level IP," said Bill Krenik, CTO of TI's wireless business unit, exposes chipmakers to greater liability if a product is recalled.

- George Leopold
EE Times





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