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Symposium reveals future of chip design

Posted: 22 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:32nm? semiconductor design fabrication? ISPD symposium?

Advances in the design and fabrication of semiconductors were unveiled last week at the International Symposium on Physical Design (ISPD). As the premier forum for sharing leading-edge results in chip-design methodologies, the ISPD also identifies future research trends years before they become commercialized. This year, topics ranged from the need for collaboration among chipmakers at the C node, how logic-synthesis is solving problems with physical-synthesis, how radio-frequency interconnection strategies could enhance standard CMOS, to how the Taiwanese beat both the U.S. and Europeans in the ISPD Global Routing Contest.

The keynote address was given by Antun Domic, senior VP and general manager at Synopsys Inc. According to Domic, all the major semiconductor makersexcept Intelneed collaborative help to be successful in manufacturing at the 32nm node.

"I'm not saying that Texas Instruments or NXP or the others will have to go fabless. What I'm saying is that instead of doing 32nm themselves, they will need to share that process development with others, and then transfer the finished process to their own fabs. Of course, I don't think Intel needs help, but the IBM-led consortium [with Samsung Electronics, Infineon Technologies, STMicroelectronics, Chartered Semiconductor, Freescale, and Toshiba] is an example of what every semiconductor maker, except Intel, needs to do to get to the 32nm node," said Domic.

Apparently verifying Domic's prediction, IBM and its partners recently claimed their jointly developed 32nm process will use high-k dielectrics to trump the rest of the industry in speed and power consumption.

Of course, not all predictions made at ISPD have come to pass. In fact Domic begged to differ with past-ISPD keynote speaker, Magma Design Automation CEO Rajeev Madhavan, who predicted "The Death of Logic Synthesis" in his 2005 address. Madhavan's point was that the preliminary circuits cast by logic synthesis could not accurately simulate the problems that would have to be faced when the circuit was physically implemented during the physical-design step, thus the solution to more and more problems were being delayed until physical design. If that trend continued, Madhavan argued, logic synthesis would eventually disappear into physical design. But, according to Domic, just the opposite has happened.

"What we are seeing today is a revival of logic synthesis," said Domic. "Physical synthesis is not just place-and-route anymore, but is being used together with logic synthesis. The two are becoming interleaved, along with design-for-manufacturability issues, giving designers more leverage."

The "Best Paper" award seemed to confirm Domic's thesis, by rewarding University of Michigan professors Igor Markov and Valeria Bertacco for their work on interleaving logic- and physical-synthesis. Markov and Bertacco showed how to use functional simulation and logic restructuring in a way that improves delay times without iterative design optimizations.

"Today, poor scaling in interconnects often necessitates many design optimizations to meet performance specifications due to the difficulty of estimating delays," said Markov. "Our solution to this problem is to identify interconnects amenable to optimization through logic restructuring and to use an algorithm to show which placed subcircuits hold the greatest promise for interconnect reduction."

'Best Paper' award
Markov and Bertacco were given the "Best Paper" award by a steering committee that included industry experts from Cadence, IBM, Intel and Magma. According to the steering committee, Markov and Bertacco combined logic- and physical-synthesis in a novel new way that provided a concrete example of how logic synthesis was alive and well.

"One of the nice elements of this work is that it's a useful integration of two different domains," said steering committee chair, Patrick Madden, professor at SUNY, Binghamton. "They have merged a couple of tasks that would normally be viewed as independent, and shown that this can give a significant benefit."

The ISPD program chair, IBM Austin Research Laboratory researcher Gi-Joon Nam, also concurred that melding logic- and physical-synthesis is the wave of the future in chip-design practices.

"Normally, lots of efforts are made during the back end of physical synthesis flow to clean up timing violations," said Nam. "Markov [and Bertacco] avoid this issue with a simulation-based method instead of thorough BDD [balancing domain decomposition] equivalence checking. The bottom line is that they have bridged the gap between logic synthesis and physical synthesis."

Another paper of note, according to general chair David Pan, an EE Professor at the University of Texas, was one showing how to create ultra-high-speed on-chip interconnects using RF transmission lines. This was presented by Professors Frank Chang and Jason Cong of the University of California at Los Angeles (UCLA). In this interconnect scheme, data is transmitted by modulating an electromagnetic wave along an RF transmission line that can be implemented using standard CMOS processing steps.

"Its advantages compared with conventional wiring include low-latency, low-power and reconfigurability" said Pan. "If RF interconnect becomes mainstream, this technique will solve many physical-design problems."

Pan and Nam were also instrumental in creating a suite of 16 routing benchmarks used to judge this year's ISPD "Global Routing Contest." Eleven entries were received this year from four countries. Four each were received from the U.S. and Taiwan, two from Hong Kong and one from Germany. Two awards were given for first and second places, both of which went to Taiwanese researchers.

"The important thing to me," said Nam, "is that every team made significant improvements over the entries from last year. Not only were they able to achieve better quality results, in terms of less overflow and better wirelengths, but the runtime of these global routers improved noticeablyup to 10-times better than last year."

- R. Colin Johnson
EE Times

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