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TI announces full production release of DDR3 register

Posted: 23 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:phase locked loop? PLL DDR3 register? registered buffer?


Texas Instruments Inc. claims the industry's first full production release of a PLL integrated DDR3 register for registered dual in-line memory modules (RDIMMs). This device enables system stability through constant clock and output delay overvoltage and temperature variation. The single-chip quad rank support saves overall board space and reduces power consumption in servers, work stations and storage equipment.

The SN74SSQE32882 28-56bit registered buffer operates at 1.5V VDD and supports parity features to ensure reliability. It provides flexibility by supporting high data rates of 800Mbit/s to 1,333Mbit/s and can support up to 72 DRAMs on one module.

Other key features include CKE power down, control mode register, output driver strength control and operating frequency of 300-670MHz.

The SN74SSQE32882 exceeds the requirements for stability overtemperature and voltage defined by the JEDEC. This ensures reliability in high-performance server systems, claims TI.

"TI is pleased to offer the first qualified and fully compatible DDR3 register to the market," said Nick Hassan, general manager of TI's Interface and Clock products group. "By working with leading industry partners, TI has designed the SN74SSQE32882 to exceed the stringent performance and stability requirements of DDR3 systems."

TI's DDR3 register adds to a complete portfolio of leading DDR2 registers and PLL devices such as the CDCUA877 and SN74SSTUB32866. In addition, the TPS51116 and TPS51100 DC/DC controllers significantly reduce the number of external components that support all the power management requirements for DDR systems.

The SN74SSQE32882 is available now in a 176-ball MicroStar BGA package. Suggested resale pricing in 1,000-unit quantities is $5.90.

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