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DRAMs get beefed up

Posted: 24 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM market? memory? DDRA2? DDR3?

Die photo of Micron DDR3!SI# 19770
The latest Micron DDR3 DRAM analyzed by SI shows the smallest DDR3 chip size.
The recent analysis of the latest DDR2 and DDR3 DRAM devices has revealed a couple of interesting trends. DRAM manufacturers, responding to harsh DRAM market conditions, are now offering more-efficient designs for both the mainstream DDR2 market and the next-generation DDR3 market.

According to DRAMeXchange, the overall DRAM market was extremely unfavorable throughout 2007, burdened by less-than-ideal demand and excess capacity from newly completed plants. These factors caused DRAM prices to fall below variable cost at one point in Q4. The average price of 512Mbyte, 667Hz DDR2 devices fell 55 percent in 2007, compared with the average price in 2006. When industry sources revealed that even a DRAM maker operating with 12-inch facilities on a 70nm process would still come out at a loss, this losing proposition sped up the retiring of 8-inch facilities from the production of commodity DRAM.

80nm vs. 90nm
Semiconductor Insights (SI) reported DDR3 analysis results based on some of the early products of Micron, Qimonda and Samsung. The report, published on May 7, 2007, and Sept. 3, 2007, revealed that overhead of enhanced speed and low power consumption of DDR3 over DDR2 was between 22 percent and 23 percent in the 90nm and 80nm process nodes.

A comparison can be made based on Samsung and Qimonda DRAM data with 80- and 90nm processes, respectively. Cell efficiency for DDR3 designs ranges from 33 percent to 45 percent, but cell efficiency for DDR2 designs of the same process technology is much higher (from 41 percent to 54 percent). A wide internal data bus and its related circuitry, including data read/write amplifier and multiplexing circuits to support 8bit prefetch architecture, consume precious silicon area. Extra pipeline stages to support high-speed I/O operations and improved on-die termination circuitry, as well as other features introduced in the DDR3 standard, contribute to this die size overhead.

With less than the highest possible operating frequency (1.6GHz) and a steep premium, and with performance-enhanced DDR2 parts on the market, DDR3 DRAM made little progress in 2007.

'Smallest' DDR3
One DRAM manufacturer's reaction to this situation is noteworthy. The latest Micron DDR3 DRAM analyzed by SI shows the smallest DDR3 chip size!one very comparable to that of DDR2.

The area overhead of DDR3 compared with DDR2 almost disappeared in Micron's 6F2 78nm, 1Gbyte DDR3 DRAM (with x8 organization). Industry sources say this particular design has been optimized for x8 and x4 only. By removing x16 options, Micron's 1Gbyte DDR3 design appears to have achieved "die area parity" with DDR2. This is a significant development in the DRAM market, which expects to make the DDR2-to-DDR3 transition sometime between 2009 and 2010.

DRAM market transition

Another notable change seen in the latest designs from Micron is a pronounced similarity across the board. As companies gain more experience working with DDR3 designs, designers are finding ways to reuse many design blocks and techniques to reduce development cost, ease device analysis and produce more-efficient designs. Two very similar floor plans, for example, were used in Micron's latest 78nm DDR2 and DDR3 devices.

Recent research shows that 6F2-cell-based DRAM is approximately 13 percent smaller in chip size than 8F2, and that it is accompanied by about a 15 percent increase in the number of gross dice per 12-inch wafer.

Although the 6F2-cell advantage of 25 percent less area is reduced somewhat to get 15 percent more dice per wafer, this increase in the number of gross dice is pivotal in maintaining the profitability and competitiveness of DRAM manufacturers.

Traditionally, Micron has used its 6F2-cell-based DRAM quite successfully. Samsung has been using its 6F2 cell in the 90-nm and 68-nm process nodes. In the recent DRAM market!in which prices have dropped more than 50 percent in a year!Qimonda's new road map to 6F2-cell-based and even 4F2-cell-based DRAM products is hardly surprising.

Die photo of Hynix DDR2!SI# 19359
Hynix's 66nm, 1Gbyte DRAM has only a 4 percent larger die area and a 4 percent lower gross number of dice per 8-inch wafer.

One DRAM manufacturer stands out as an exception to this trend (at least as of today): Hynix. As the second-biggest manufacturer in the worldwide DRAM market, how does Hynix's technology compare with Samsung's and Micron's more-efficient 6F2-cell-based DRAM technologies?

Recent analysis conducted by SI on two comparable DRAM devices from Samsung and Hynix might shed some light on this question. According to SI, Hynix's 66nm, 1Gbyte DRAM (128Mbyte x8) is an impressive design, having only a 4 percent larger die area and a 4 percent lower gross number of dice per 8-inch wafer. This is a significant improvement over its 80nm, 512Mbyte DRAM design, which suffered a 15 percent reduction in the number of gross dice per 8-inch wafer compared with Samsung's 80nm, 512Mbyte 6F2-cell DRAM design. Hynix's lack of a 6F2-based cell must have forced the company to pursue more-aggressive process node scaling (66nm, as apposed to Samsung's 68nm), and to rely on innovative design and layout. Judging from a chip-size and gross-dice perspective, SI believes this design to be very competitive with comparable designs from both Samsung and Micron.

Chip size overhead of DDR3 over DDR2 (relative comparison)

Aggressive scaling, combined with clever design and layout, reuse of circuit blocks and architectures and the optimization of certain features to develop more-efficient DRAM products, plays a significant role in the survival of DRAM manufacturers with different technologies in today's harsh commodity DRAM market. These efforts will enable and accelerate the market's transition from current DDR2 to next-generation DDR3, expected within the next year or two.

- Young Choi
Memory Technology Manager
Semiconductor Insights

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