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Spice tool addresses chip design bottleneck

Posted: 25 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:simulation? IC design? Spice simulator?

At its 2008 Technology Symposium, Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) moved to address a bottleneck in chip design: simulation.

Silicon foundry giant TSMC rolled out its so-called Spice Tool Qualification Program. The program includes a simulation kit, models and a third-party reference guide.

The program is said to drive its third-party design ecosystem to develop Spice simulators ''with greater accuracy and higher performance.''

Targeting TSMC's 65nm node and beyond, the company will endorse a selection of qualified Spice simulators from third-party providers. Once a Spice simulator passes qualification, TSMC will post a qualification report on TSMC-Online, the company's Web portal.

Multiple EDA partners are already participating in the program including Agilent Technologies, Berkeley Design Automation, Cadence, Magma, Mentor, Simucad and Synopsys.

TSMC is also introducing iSDK, a Spice design kit, along with TSMC's Model Interface (TMI) technology. Written in standard C language, iSDK with TMI is a new method for compact SPICE device modeling that is an addition to the traditional and slower macro modeling approach, said S.T. Juang, senior director of design infrastructure marketing at TSMC.

"Going beyond the traditional tool qualification program, TSMC's Modeling Interface architecture sets a new standard in Spice modeling accuracy and simulation efficiency,'' he said. ''The program provides designers the ability to select qualified Spice simulators to match their design needs, improve compliance with TSMC processes, and ensure design accuracy for first time silicon success."

- Mark LaPedus
EE Times

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