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DDR memory controller ups efficiency by 20%

Posted: 29 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:DDR memory? controller chip? system efficiency?

Virage Logic Corp. has announced that the Intelli DDR memory controller interface can provide up to a 20 percent efficiency gain for high-performance applications, while still maintaining low-power. Architected from the ground up to provide a combination of low-latency, high-performance and low-power options, the Intelli DDR solution incorporates intelligent scheduling algorithms for superior system bandwidth.

High efficiency gains deliver significant benefits for both high-performance and low-power customers. As an example, a customer with high-performance requirements can benefit from a 20-percent efficiency gain resulting in up to a 20-percent greater data throughput at the same frequency. A low-power solution delivering a 20-percent efficiency gain means that customers can expect to realize up to a 20 percent reduction in clock frequency at the same data rate, leading up to a 20-percent reduction in dynamic power. In certain low-power applications where packaging cost limitations prevent extremely high-frequency operations, customers can achieve desired results with higher-efficiency DDR protocols.

"Virage Logic's Intelli DDR solution provides the maximum performance at the minimum clock frequency, making it an ideal choice for a broad spectrum of market segments ranging from networking to consumer-based mobile solutions," said Kamalesh Ruparel, VP and general manager of application specific IP (ASIP) solutions and silicon technology at Virage Logic. "Compared to other commercially available solutions benchmarked across several market segments, Virage Logic's Intelli DDR solution consistently delivered higher data throughput efficiency ratings."

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