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TSMC throws hat in 32nm high-k ring

Posted: 29 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:high-k plan? metal gates? 32nm node? CMOS?

Taiwan Semiconductor Manufacturing Co. Ltd has unveiled new derivatives of its 40nm process and outlined details of its 32nm road map, giving an impression that the foundry giant may be playing catch-up with its foundry rivals, particularly in the emerging arena of high-k materials and metal gates.

IBM Corp. and its foundry partners recently tipped plans to offer high-k and metal gates to customers at the 32nm node in 2H 09, and has presented various papers on its technology. In contrast, TSMC has not disclosed technical details on high-k and metal gates, leaving some to wonder if the silicon foundry giant is falling behind.

Jack Sun, VP of R&D at TSMC, said the company would not be late to the party for high-k/metal gate. Sun said the company would provide various gate-stack options at the 32nm node.

Leading edge
But process technology is far from the only concern for TSMC and other foundries. During a keynote address at last week's TSMC 2008 Technology Symposium, Andy Rappaport, a partner in August Capital, cited a paradigm shift that has IC designers "rethinking" their transistor budgets and system architectures.

In the past, foundries would develop a particular leading-edge process and chipmakers would flock to it, rushing out devices based on the technology. But as design costs soar at each node, the emphasis is generally shifting from a raw transistor count on a complex IC to better use of those transistors, Rappaport said.

Chip designers may be looking at utilizing fewer transistors in products, a trend that runs somewhat counter to the leading-edge foundry model.

"There is less of a push toward the leading edge" in the foundry world today, concurred Bryan Lewis, an analyst with Gartner Inc. Developing devices based on leading-edge processes is risky, Lewis said, so "you have to look at the overall design costs and [anticipated] volumes" before moving to the next process node.

In general, IC design costs today range between $20 million and $50 million. At the 32nm node, design costs could hit an estimated $75 million per product.

Nevertheless, a significant group of chipmakers still embraces the leading edge, said Jason Chen, VP of worldwide sales and marketing for TSMC. "There are applications that do not follow Moore's Law," Chen told EE Times. "But we are still seeing PC graphics chipmakers and others taking advantage" of leading-edge technology.

Last month, TSMC rolled out its most advanced process: a general-purpose 40nm technology. So far, TSMC has publicly identified only Altera Corp. as developing a part based on the process. Another customer, Qualcomm Inc., has been talking about an undisclosed part based on TSMC's 45nm technology.

High-k race
Also of concern to TSMC is the general state of the IC industry, along with competitive threats from IBM's "fab club" and other emerging rivals. On the business front, the foundry sector is expected to hit $24.6 billion this year, up 11 percent over 2007, according to Gartner.

But the subprime mortgage crisis, bloated inventories and lackluster demand are casting a shadow over the overall IC business. Rick Tsai, president and CEO TSMC, predicted the semiconductor market would grow a modest 4 to 5 percent in 2008.

Over the years, TSMC and its chief rival, United Microelectronics Corp., have raced each other to provide the world's most advanced foundry processes at each node. Rarely have they lagged the other foundry vendors in technology. But that may have changed.

This month, IBM and its foundry partnerssuch as Singapore's Chartered Semiconductor Manufacturing Pte Ltd, South Korea's Samsung Electronics Co. Ltd and Japan's Toshiba Corp.said they would have access to IBM's high-k/metal-gate technology at the 32nm node in 2009.

The group claims the technology delivers 35 percent better performance than circuits built in 45nm at the same operating voltage. The 32nm technology also consumes 30-50 percent less power with respect to operating voltage.

"The benefit for fabless CMOS companies is that they now can have the performance gains of a high-k/metal-gate process," Gartner analyst Dean Freeman said in a newsletter. "However, design and initial manufacturing at the 32nm technology node will be fairly expensive."

So far, Intel Corp. appears to be the only chipmaker shipping products with high-k and metal gates. Its 45nm processors use a replacement-gate approach, as opposed to the gate-first technology favored by IBM.

TSMC is proceeding with its own advanced-node plans. For its 32nm low-power process, it intends to develop a 3G triple-gate-oxide technology. For its 32nm high-performance process, it will offer a high-k and metal-gate technology, according to TSMC's Sun.

He declined to elaborate on TSMC's high-k offering, saying only that "there's a lot of work to be done." It will be targeted for processors and other products.

TSMC will make the Sparc processor on a foundry basis for Sun Microsystems Inc. Since those future processors would most likely require a high-k gate-stack to reduce leakage, some speculate that TSMC could deploy a high-k technology created by Sun Microsystems' former foundry partner Texas Instruments Inc.

40nm rollout
TSMC also rolled out several derivatives of its 40nm technology at last week's Technology Symposium. The foundry provider's general-purpose 40nm process is shipping now. TSMC also plans to deliver a low-power version, a mobile derivative and an RF variant of the process.

The company also provided details about its 32nm process, a 10-level-metal (or higher) strained-silicon technology equipped with copper interconnects and ultralow-k dielectrics.

Like the company's 45nm process, the 32nm technology will be manufactured using 193nm immersion lithography. "Some of the critical layers will be done with double patterning," said Sun.

TSMC's high-performance 32nm process is due out by the end of 2009. A low-power version is slated for introduction at the beginning of 2010.

- Mark LaPedus
EE Times

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