Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

TSMC IC design collaboration strategy stirs controversy

Posted: 30 Apr 2008 ?? ?Print Version ?Bookmark and Share

Keywords:IC design collaboration? TSMC strategy? Open Innovation Platform?

Taiwan Semiconductor Manufacturing Co. Ltd has unveiled a new and possibly controversial strategy that involves more collaboration in the early stages of the IC design process.

TSMC's program is aimed to reduce development cycles and manufacturing costs, according to analysts. But it could also possibly cause a major stir in the industry, as the silicon foundry giant wants more of the IC pie and appears to be encroaching on the turf in the third-party EDA, IP, packaging and test communities.

Open innovation
As part of its strategy, TSMC is quietly pushing a concept called the Open Innovation Platform (OIP), according to Gartner Inc. During its technology conference last week, TSMC also disclosed details about its roadmap in the chip-packaging front, including its internal efforts in the 3D arena.

OIP is a program that involves more "collaboration between the foundry and its clients at the early stages of the design phase," said Jim Walker, an analyst with Gartner, in an e-mail newsletter.

TSMC's OIP consists of a platform of design tools and IP to help customers with their design-to-manufacturing efforts, Walker said. "OIP integrates TSMC's manufacturing technologies, silicon IP, massive manufacturing database and compatible third-party silicon IP and design tools," he said.

"Through OIP, TSMC can offer vertically integrated services, from designing and manufacturing to testing and packaging, thus shortening clients' IC development processes and reducing their manufacturing costs," he said.

Concern for competitors
Many of these efforts could be viewed as competitive to TSMC's current partnerships in the EDA, IP and IC-packaging communities. For example, "this announcement should be of concern to the SATS industry companies (that is, contract assembly and test houses), such as Amkor Technology, Advanced Semiconductor Engineering, Siliconware Precision Industries Ltd, STATS ChipPAC, UTAC and others," Walker wrote. "This expansion in services could mean a potential loss of business for these SATS companies from TSMC's new internal packaging operations."

On the surface, the strategy makes sense, other analysts said. As design and manufacturing costs continue to soar at each node, TSMC is providing more tools to help chipmakers develop their products. In other words, TSMCand other foundriesare providing more of a one-stop shop of services to help customers.

Besides its internal and massive front-end manufacturing capabilities, the foundry giant already offers a complete IC design flow, which includes a plethora of qualified third-party EDA tools and intellectual-property (IP) blocks.

TSMC also provides limited IC design services. And for years, TSMC has invested in the development of IC-packaging and test technology. The company provides some of these back-end services in-house, but it generally hands off the production capabilities to third-party subcontractors.

But as it develops more of the value chain in-house "such as EDA tools, IP blocks, IC-packaging and test" TSMC is stepping on the toes of its partners.

Rationale
One theory behind TSMC's motives is that the company wants more of the semiconductor pie to offset a slowdown in the overall foundry business. For years, the foundry business saw explosive growth due to the ongoing outsourcing trends in the marketplace. Last year, though, the foundry sector hit $22.191 billion, up only 2.5 percent from 2006, according to Gartner.

TSMC's sales hit $9.828 billion in 2007, up only 1.2 percent over 2006, according to the firm. The company still dominated the foundry sector, as it owned 44.3 percent share of the business in 2007, according to Gartner. Rival United Microelectronics Corp. was second with 14.7 percent share in 2007, followed in order by SMIC (7 percent), Chartered (6.5 percent), IBM (2.7 percent), Vanguard (2.2 percent), X-Fab (1.9 percent) Dongbu (1.8 percent), MagnaChip (1.7 percent) and Hua Hong NEC (1.4 percent), according to the firm.

Besides a slowdown in sales, TSMC is developing its own, internal capabilities for other reasons. First, by developing its own IP, TSMC can lock foundry customers into its own, internal fabs. For example, TSMC's third-party IP is portable and works across several competitive foundries. In contrast, TSMC's physical IP is proprietary and does not work in competitive fabs.

Second, there is a fear inside TSMC that the third-party EDA, IP and IC-packaging houses are unable to keep up with Moore's Law and the company's process-technology offerings. So in an effort to hedge its bets, the company must develop its own IP to make sure there is an offering tailored for its own processes.

In any case, TSMC is moving down the vertically-integrated path in spite of what its partners say. For some time, TSMC has been developing its own physical IP blocks, which compete against those from its partners, such as ARM, Virage and others.

Last week, TSMC took a step in the EDA world by rolling out a SPICE Tool Qualification Program. The program includes a simulation kit, models and a third-party reference guide. Besides endorsing third-party simulation tools, TSMC is also introducing iSDK, a SPICE design kit, along with TSMC's Model Interface technology. Written in standard C language, iSDK with TMI is a new method for compact SPICE device modeling that is an addition to the traditional and slower macro modeling approach.

Package production
For years, TSMC has offered a range of backend services for customers: wafer sort, bumping and limited flip-chip packaging. Then, in 2007, the company invested $59.7 million in wafer-level packaging technology.

"As optimization of silicon functionality becomes more interdependent on the packaging technology used, this announcement (about OIP) seems logical," Walker said. "This updated announcement (about OIP) expands more on the previous announcement. TSMC is now offering more vertically integrated services, including broader packaging and test services."

TSMC does not pretend to be a full-fledged IC-packaging or testing subcontractor. T.W. Karta, senior director of backend technology and services at TSMC, said the company continues to work with third-party subcontractors, such as Amkor, ASE, ChipPAC and SPIL.

But according to TSMC's roadmap, the company is putting more resources into two areas: stacked die packages and 3D.

It is unlikely TSMC will mass produce stacked packages. But to help the subcontractors and customers, TSMC has internally developed 65nm wirebond and flip-chip chip-scale packages. In 2009, it will develop those technologies for the 45nm node.

TSMC also has a keen interested in wafer-level packaging. This is 3D or so-called through-silicon-via technology. Whether or not TSMC will mass produce 3D package remains to be seen.

Right now, the company currently offers the so-called PT140, a post through-silicon-via technology with a 140?m pitch.

By the end of 2009, TSMC will offer PT60, a post through-silicon-via technology, with a 60?m pitch. And in 2010, it will develop IT17, an in-process through-silicon-via technology at a 17?m pitch.

Karta declined to comment if TSMC or the subcontractors will produce 3D packages. On its roadmap, TSMC has described its wafer-level packaging technology as a ''volume service.''

- Mark LaPedus
EE Times





Article Comments - TSMC IC design collaboration strateg...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top