Row boundary crossing functionality in CellularRAM memory

Micron's CellularRAM devices are designed to be backward-compatible with 6T SRAM and early-generation asynchronous and page PSRAM, and are based on a fixed row size. Memory controllers must handle boundary crossings between consecutive rows.

This technical note describes the conditions that exist at the row boundary for the WAIT pin and burst read/write operations, focusing on row boundary crossing as supported on CR 1.0-compliant devices. RBC support on other Micron PSRAM devices is discussed in Appendix A on page 13.

View the PDF document for more information.