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Processing engine works with FPGA mezzanine card standard

Posted: 01 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:engine processing VMETRO? FPGA? Xilinx?

VMETRO introduces one of the industry's first FPGA processing engines with support for the FPGA Mezzanine Card (FMC/VITA 57) standard.

The FPE650's design integrates four Xilinx Virtex-5 FPGAs with two FMC I/O sites and VPX high-speed serial backplane connectivity, allowing I/O and processing capabilities in a single 6U slot. The FPE650, available in air-cooled and conduction-cooled rugged versions, is designed to tackle demanding digital signal processing applications such as Electronic Counter Measures (ECM), Signal Intelligence (SIGINT) and Electro-Optics (EO).

At the heart of the FPE650 are four fully inter-connected user programmable Xilinx Virtex-5 FPGAs. The FPGAs sites can be fitted with Virtex-5 SX95T, LX155T or FX100T platforms enabling the FPE650 to be optimized for DSP or logic centric designs. Each FPGA has four directly connected banks of memory to maximize performance. Two of the FPGAs interface to four banks of 9Mbytes QDR2 SRAM memory; the other two FPGAs interface to two banks of 9Mbytes QDR2 SRAM memory and two banks of 640Mbytes DDR2 SDRAM memory.

The FPE650 addresses the I/O and data bandwidth requirements of high performance digital signal processing applications with three interconnects featuresthrough FPGA Mezzanine Card (FMC/VITA 57) sites for front panel I/O, through a non-blocking crossbar to help optimize the FPGA topology, and VPX/VITA 46 connections for backplane I/O. For front-panel I/O, each FMC site has 68 differential signal pairs supporting 2Gbit/s data rates per pair and four full duplex multi-Gbit/s connections to enable very large amounts of data to be moved between FMC modules and the on-board FPGAs. For on-board data movement, high-speed serial links from the FMC sites, the FPGA, and the backplane are routed to a non-blocking crossbar switch.

By configuring the crossbar switch, the connections between these resources to be configured specifically to meet application needs. For backplane I/O, each FPGA has two x4 full duplex multi-Gigabit/sec serial ports routed to the VPX backplane with each x4 port able to move over 1GBps of data. The FPE650 also provides backplane parallel I/O directly connected to two of the FPGAs.

VMETRO will be announcing a range of FMC modules shortly to be used with the FPE650 and other VMETRO FPGA-based products. Price for the FPE650s start at $30,000.

- Ismini Scouras
eeProductCenter





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