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Work underway on mobile DRAM interface spec

Posted: 02 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:DRAM? mobile devices? memory interface? standards definition?

An organization dubbed the Serial Port Memory Technology (SPMT) Working Group has been formed to devise an open standard for a next-generation DRAM interface technology in mobile products. Members include ARM, Ericsson, Hynix, LG, Silicon Image, Samsung, Sony Ericsson Mobile and STMicroelectronics.

But the group appears to be missing some key processor and DRAM vendors, notably AMD, Elpida, Intel, Micron, Qimonda and others.

Still, the SPMT Working Group is moving full speed ahead and hopes to establish a high-speed, multiport serial interface for DRAMs in the mobile space. If it flies, the market is expected to see a new class of DRAMs for the mobile market.

Dubbed SPDRAMs, the products are said to have some advantages over current technology. Current DRAMs in the mobile space are said to utilize a parallel interface technology. Parallel technology is "difficult to design" and "consumes a lot of power," said Anu Murthy, senior technology marketing manager for Silicon Image.

Jim Venable, head of Silicon Image's Advanced Memory Technology Products, said there are other advantages to the new technology proposed by the SPMT group. The technology reduces pin count, lowers power consumption and enables multiple ports by using a serial interface instead of the parallel interface, he said.

This technology is ideal for mobile handset manufacturers who are incorporating more media-rich features at lower system cost, according to the group.

The Working Group intends to form the SPMT Consortium some time in the Q3 08, although the timing may change. Once the SPMT specification is ratified by the consortium, it will be made available to the industry through the SPMT Consortium, with licensing terms yet to be decided by the SPMT Working Group.

It is unclear if the working group is considering participation in other groups, such as the Mobile Industry Processor Interface Alliance (MIPI). ''Over the next several months, the working group will address how SPMT will fit into other industry initiatives, both opportunistic and synergistic,'' the group said.

Concrete goals
Overall, the SPMT Working Group's goal is to define a memory interface technology that reduces pin count by a minimum of 40 percent and cuts input/output power by 50 percent or more over other currently available DRAM offerings.

According to the group, SPDRAM technology, equipped with the new interface, will have some advantages over one of the latest flavors of mobile DRAMs in market, most notably LPDDR2 technology.

With the new interface, SPDRAM technology is said to have a bandwidth of 200MBps to 12.6GBps, according to the group. In comparison, LPDDR2 is said to have a bandwidth of 200MBps to 3.2GBps.

The SPMT specification also defines a system with 10 signal pins at 800MBps and 20 signal pins at 3.3GBps. I/O power is 40mW at 800MBps and 120mW at 3.3GBps.

- Mark LaPedus
EE Times

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