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VeriSilicon signs up with Power Forward Initiative

Posted: 14 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:Power Forward Initiative? Common Platform Format? ASUC design?

ASIC design foundry VeriSilicon Holdings Co. Ltd has joined the Power Forward Initiative and plans to offer a Common Power Format (CPF)-based design solution for its ASIC customers.

VeriSilicon uses Cadence Design Systems Inc.'s Low-Power Solution that integrates logic design, verification and implementation technologies with the Si2-approved CPF. Using this approach to low-power design, teams can improve productivity, reduce risk and achieve superior tradeoff among timing, power and area requirements.

"Low-power design is critical for multimedia, wireless and communication applications," said Nianfeng Li, corporate VP of design methodologies at VeriSilicon. "We have joined the Power Forward Initiative to contribute our low-power expertise in support of the broad, industry-wide move to low-power electronic design. VeriSilicon has worked with Cadence to deploy this advanced low-power solution for our ASIC customers. We expect that CPF will streamline the entire low-power design process to help customers meet their market requirements on time."

"VeriSilicon, with its focus on the fast growing market in China, brings a unique perspective to the Power Forward Initiative. Their participation will help accelerate the use of low-power technologies in the industry," said Pankaj Mayor, group director of business enablement at Cadence.

CPF, an Si2-approved standard format, is used for specifying power-saving techniques early in the design processenabling sharing and reuse of low-power intelligence throughout the design process. The Cadence Low-Power Solution is the industry's first complete flow that integrates logic design, verification, and implementation with the Si2-standard Common Power Format.

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