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Serdes chipset claims 'best' jitter performance

Posted: 15 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:serializer? deserializer? Serdes chipset?

National Semiconductor Corp. has introduced a Serdes chipset that the company claims delivers the industry's best output jitter performance of 35ps peak-to-peak and the best input jitter tolerance of 0.9 units interval (UI) with a BER of 10-15. The Serdes chipset serializes data up to 3.125Gbit/s and is well suited for industrial and medical imaging, communications infrastructure, commercial displays, and test and measurement systems.

Details, features
The highly integrated chipset includes the DS32ELX0421 serializer and DS32ELX0124 deserializer. They feature advanced on-chip signal and clock conditioning circuitry that extends the data transmission reach of CAT-6 (shielded 23 AWG) cable beyond 20m. The Serdes also support a variety of interconnect media including CAT-5 cable, optical fiber, 50 or 75 coaxial cable and FR-4 backplanes.

The Serdes' unique architecture replaces the traditional wide single-ended parallel bus with a 5bit low-voltage differential signaling (LVDS) interface. This interface simplifies board layout by reducing the number of I/O pins and traces between the serializer, deserializer and FPGA. In addition, the LVDS interface reduces EMI, while enabling the use of low-cost FPGAs in a variety of high-speed, high-performance applications.

The Serdes' redundant I/Os and retimed active loop-through enable advanced system configurations such as failover, link aggregation and daisy chaining. Power consumption is less than 1W, and both devices include an automatic standby mode using signal detect and a configurable sleep mode for additional power savings. Both devices are offered in a 48-pin LLP package.

The DS32ELX0421 serializer includes a DDR 5bit LVDS parallel data interface and a redundant serial output channel. The integrated jitter cleaning PLL accepts a 125MHz to 312.5MHz input clock for a serial data rate of 1.25Gbit/s to 3.125Gbit/s. The DS32ELX0421 allows programming of transmit de-emphasis levels, output voltage levels and selection of DC-balance encoding. This programming flexibility enables the use of DS32ELX0421 in a wider range of interconnect media and applications compared to existing serializers, National said. A remote sensing feature automatically detects and negotiates link status with the companion DS32ELX0124 deserializer. The DS32ELX0421 typically consumes 470mW of power at 3.125Gbit/s.

Details, features
The DS32ELX0124 deserializer includes a DDR 5bit LVDS parallel interface, redundant serial input and retimed serial output channel. The DS32ELX0124 deserializes up to 3.125Gbit/s of high-speed serial data to five LVDS outputs without the need for an external reference clock. The DS32ELX0124 offers programmable receive equalization, and a minimum jitter tolerance of 0.9 UI. A remote sensing feature automatically signals link status conditions to its companion DS32ELX0421 serializer for intelligent link management. The DS32ELX0124 typically consumes 525mW of power at 3.125Gbit/s.

In addition to the DS32ELX0421 and DS32ELX0124, National also offers the DS32EL0421 serializer for applications that do not require a redundant serial output channel and the DS32EL0124 deserializer without a redundant serial input and a retimed serial output channel.

National also offers reference IP and design guides for interfacing FPGAs to the DS32ELX0421 and DS32ELX0124. As part of its FPGA IP package, National includes a BER test engine for test pattern generation/validation and system-level functions such as link aggregation and failover.

All available now, the DS32ELX0421 serializer and DS32ELX0124 deserializer are priced at $18 each in quantities of 1,000. The DS32EL0421 serializer without redundant output channel and the DS32EL0124 deserializer without redundant input and retimed output channel are $14 each in quantities of 1,000.

- Gina Roos

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