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Cut down processor power consumption with CPLD

Posted: 16 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:CPLD? power? processor? processor power consumption?

One of the most critical factors in designing portable electronics today is reducing overall system power consumption.

With increased consumer expectations, portable devices require longer battery life and higher performance. Even power reductions on the order of 10mW are crucial to portable system designers and manufacturers.

Reducing power consumption involves correct management of the operating mode of a device and designing a system to take advantage of the modes a device can operate within. Offloading operations of the microprocessor allows it to stay in its low-power state for a longer amount of time. One way to reduce system power is to allow a low-power PLD, such as a CPLD, to manage these offloaded operations. This article describes this possibility, along with types of operations that allow a processor to remain in a low-power state longer, thereby reducing system power consumption.

View the PDF document for more information.





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