New formula to speed up PCB designs

Each new generation of silicon like 90nm and 45nm brings a set of end-user benefits such as lower cost, lower power and new functionality. It also brings new PCB design-in challenges like smaller footprints, simultaneous switching noise and faster edge rates. These challenges translate into a set of new constraints for designing a PCB.

Over the past decade, the number of nets on a PCB that have constraints has gone up significantly, sometimes approaching 100 percent of nets on a PCB. New I/O interfaces such as DDR2, DDR3 and PCIe make it easier to design a PCB. However, these I/O interfaces also add constraints on how they should be designed at the physical level. Increasing number of constraints, if not handled properly, can extend the PCB design cycle and worse, require physical prototype iterations that also add material costs.

PCB designers need a methodology that can help them avoid design iterations between the design and layout stages, or finding issues with the board in the lab with a physical prototype. This article discusses how a "correct-by-construction" PCB layout methodology can help PCB designers shorten their design cycle.

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