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Take your pick of NAND implementation

Posted: 16 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:SLC MLC NAND? NAND implementation options? embedded applications storage?

NAND flash has become the prevalent choice for mass storage in consumer applications due to its lower cost per bit and higher density advantages over NOR flash. Moreover, NAND has a smaller size, less power and has robust advantages over HDDs.

As the demand for increased NAND flash density surges, designers are faced with the challenge of selecting from a variety of NAND flash types, densities, vendors, roadmaps and implementations.

Selection criterion
The first and most important selection criterion for using NAND flash is the implementation of the NAND controller. All NAND flash devices require maintenance overhead located in the software and hardware of an external controller to ensure reliable data, maximize the lifespan of the NAND flash device and to enhance performance. The three main functions of the NAND controller are bad block management, wear-leveling and error correction coding (ECC).

NAND flash stores memory in clusters called blocks. Most NAND flash devices will inherently be built with some bad blocks that will be found upon testing conducted during manufacturing. These blocks will be labeled as bad in the device specification by the vendor.

Good blocks may degrade over the life cycle of the NAND and must be tracked via software (bad block management). Additionally, consistent reads and writes to a particular block may cause the block to "wear out" and become a bad block. To maximize NAND life and limit the amount of blocks that wears out, all blocks should be read and written to evenly in a process called wear-leveling.

Bit errors may occur due to inactivity or operation of a particular cell, and ECC must be implemented in either software or hardware to detect and correct these errors. ECC is typically defined by the industry as the number of bits the code can correct per 528byte sector. In a system, this NAND controller can be combined with the NAND in three different implementation options, as shown in the figure.

In conjunction with selecting from the three options of NAND solutions, a designer must also choose between two types of NAND flash devices: single-level cell (SLC) NAND and multilevel cell (MLC) NAND. Each offers its own benefits.

SLC NAND provides longer life cycle and reliability of each block, therefore requiring less ECC and offering superior performance. MLC NAND requires higher levels of bad block management, wear-leveling and ECC. However, MLC NAND is also roughly one-third of the price of SLC NAND per bit.

Implementation options
In platforms where designers are using a microprocessor that has a full NAND interface and controller, Option 1 is typically the preferred choice. Most contemporary microprocessors, if they have any support for NAND at all, typically only support SLC NAND in lower densities. The process technology limits the amount of storage on a die of SLC or MLC NAND, as currently this density is at about 1Gbyte of storage per die. Thus, to support higher densities of NAND, a controller must be able to support multiple NANDs. This is usually done using an interleaving process and multiple chip-enables.

Currently, the levels of ECC needed for MLC NAND are at 4bits, but are quickly moving to 8bit and 12bit. The higher amounts of ECC require hardware in the NAND controller. However, microprocessor evolution is proceeding at a slower pace than the rapidly evolving MLC NAND.

When considering the combination of requirements for a system's NAND budget, designers have several NAND implementation options.

The "controlled NAND" approach (Option 2) is useful with many different embedded and removable types of storage. All portable SD/MMC cards use this type of implementation, and there are several choices for embedded controlled NANDs in the market place. This approach has its advantages, as the microprocessor only needs to support an SD/MMC type interface to add system support for either SLC or MLC NAND.

The controller is stacked with the NAND and handles all bad block management, wear-leveling and ECC for the NAND. Controlled NAND implementations are seen currently at roughly 4Gbyte densities in embedded applications and at 8Gbyte in removable cards.

The disadvantage with this approach is that each NAND vendor supports different interfaces on their variety of controlled NAND, and switching from one NAND vendor to another requires a complete software overhaul.

Option 3 gives designers the most flexibility in choosing the type of NAND and in choosing from different vendors. Almost all NAND controllers support different types, vendors and densities of NAND. Because the NAND controller will always use the same interface to the processor, the designer is free to choose different types and vendors of NAND without having to change any software.

Stephen Harris
Product Manager
Cypress Semiconductor Corp.

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