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Altera claims industry's first 40nm FPGAs, ASICs

Posted: 20 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:40nm? FPGAs? ASICs?

Enabling designers to achieve new levels of integration and innovation, Altera Corp. introduces what it claims to be the industry's first 40nm FPGAs and HardCopy ASICs. The The Stratix IV FPGAs and HardCopy IV ASICs, both with transceivers options, provide unprecedented densities, performance and low-power leadership, says Altera. "Our customers have been asking us to be more aggressive," remarked Dave Greenfield, senior director product marketing, high-end FPGA products. "And the capability we are introducing is a very big step forward," Greenfield added.

The Stratix IV family has up to 680K logic elements (LEs), 2x bigger than Altera's Stratix III family. The HardCopy IV ASIC family offers equivalent densities as the Stratix IV devices and features up to 13.3 million gates. The 40nm devices meet high-end application needs such as wireless and wireline communications, military, broadcast and ASIC prototyping. "The key innovation here is the transceiver option, which allows us to play in the communications sector," explained Greenfield.

Leveraging on the solid partnership Altera has established with Taiwan Semiconductor Manufacturing Co. Ltd (TSMC), the devices were manufactured on TSMC's 40nm process. The Stratix IV FPGA family is comprised of two variants, an enhanced variant rich with memory and DSP resources (Stratix IV E FPGAs) and an enhanced variant with transceivers (Stratix IV GX FPGAs). Stratix IV GX FPGAs offer up to 48 transceivers operating at up to 8.5Gbit/s, which says Altera, provides designers with the industry's highest available bandwidth, more than twice the bandwidth of any other FPGA. Stratix IV GX FPGAs also feature hard intellectual property (IP) support for PCIe Gen 1 and 2 and also supports a wide range of protocols including, Serial RapidIO, XAUI (including DDR XAUI), CPRI (including 6G CPRI), CEI 6G, Interlaken and Ethernet.

Other innovations
To address the low-power demands of customers, the Stratix IV family members feature Altera's patented Programmable Power Technology, which optimizes logic, DSP and memory blocks to maximize performance where needed while delivering the lowest power elsewhere in the design.

"Today's announcement significantly widens the density, performance and low-power advantages of the Stratix series versus competing offerings," said John Daane, president, CEO and chairman of Altera in a statement. "Combined with the HardCopy ASIC family, Altera is the only company that can offer a complete high-performance solution that allows designers to quickly move from concept to volume production."

The company also announced enhancements to its Quartus II design software and delivered IP solutions optimized for 40nm products.

Customers can start their Stratix IV designs using Altera's Quartus II design software v.8.0. Engineering samples of the first member of the Stratix IV device family will be available in Q4. Customer tapeouts for HardCopy IV ASICs will start in Q3 09.

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