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Altera rolls Quartus II Software Version 8.0

Posted: 22 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:Quartus II? 40nm? Stratix IV FPGAs? Linux?

Altera Corp. has announced its Quartus II software version 8.0, supporting the company's 40nm Stratix IV FPGAs and HardCopy ASICs. This version of the Quartus II software delivers, on average, a full two-speed grade advantage and 3x faster compile times for high-end FPGAs when compared to the nearest competitor's latest offering. With new productivity features and support for the industry's most advanced FPGAs, version 8.0 reinforces Altera's commitment to deliver the highest level of performance and productivity to FPGA designers.

Fast compile times
Over the past five years, Quartus II software has consistently delivered the industry's fastest compile times for high-end FPGAs, averaging a 20 percent reduction annually. Customers using the 8.0 release to design Altera's 65nm Stratix III FPGAs on Windows platforms will see compile times reduced by up to 50 percent, with an average reduction of 22 percent, when compared to version 7.2. Users of Linux platforms will see average compile times decrease by more than 30 percent. Designs leveraging multiprocessor-based servers will obtain an even higher compile time advantagean additional 20 percent reduction on averageusing the industry's only vendor-supplied FPGA design software with multiprocessor support.

Quartus II software's incremental compilation feature offers users a second-to-none productivity advantage, capable of delivering up to a 70 percent compile time reduction compared to a standard compilation. Assisting designers in maximizing the full benefits that incremental compilation provides, Quartus II software version 8.0 features a new design partition planner. During the process of creating incremental compilation design partitions, an interactive GUI provides real-time feedback, such as logic resource usage and inter-partition timing paths, enabling designers to explore and quickly determine the most effective partition scheme.

"Our customers continue to emphasize the importance of FPGA design productivity in the race to get products to market," said Chris Balough, marketing director for software, embedded, and DSP at Altera. "With the release of version 8.0, Altera continues to earn our customer's confidence that they have a clear productivity advantage with Quartus II software, which they can now leverage for the industry's most advanced 40nm FPGAs."

Added features
Additional enhancements to Quartus II Software Version 8.0 include a new tasks window that provides an interactive design flow console that guides users through the FPGA design flow.SOPC Builder: Offers support for incremental compilation and adds key IP blocks to its design library, including JTAG and SPI interfaces. New floating point, delay lock loop and memory initialization megafunctions in Quartus II software also help speed design development.

Quartus II Subscription Edition software version 8.0 is available now through local Altera sales representatives and distributors. Both the subscription edition and the web edition of Quartus II software version 8.0 will be available for download on June 2. Quartus II software is also available in DVD format by request. Altera's software subscription program simplifies obtaining Altera design software by consolidating software products and maintenance charges into one annual subscription payment. Subscribers receive Quartus II Subscription Edition software, the Mentor Graphics ModelSim-Altera edition and a full license to the IP Base Suite, which includes 11 of Altera's IP cores (DSP and memory). The annual software subscription is $2,495 for a node-locked PC license.

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