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Design aidsmulticontext switch event kernel

Posted: 22 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:application note? multicontext switch? event kernel?

PSoC mixed-signal architecture features tightly coupled analog and digital blocks that often require some post processing. Blocks trigger the CPU via individual interrupt vectors. The appropriate post processing code for each interrupt is provided by an Interrupt Service Routine (ISR). If you have time-critical code, you can improve the system response time of the ISRs by selecting higher CPU clock speeds and hand coding ISRs in assembly language. However, the PSoC CPU power is limited, and this will only increase response speeds up to a point. Increasing the system clock speed also increases power consumption. If you wish to guarantee low latency system response times and reduce power consumption, you must employ a different concept of code development.

This application note from Cypress Semiconductor describes an event-based, multicontext switching micro-kernel that requires 2bytes of SRAM and minimal flash memory. An additional byte of SRAM may be reserved for system overload error detection. The microkernel is created as a separate module that you can use in existing PSoC designs. To make use of the kernel, you split your current ISRs into an ISR that is as short as possible, and a series of events. Each shortened ISR does only the necessary time-dependent IO transactions with the analog or digital blocks, and then triggers an event with an assigned priority. The event is executed as soon as all ISRs and events with higher priority have completed.

View the PDF document for more information.

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