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Interfacing LVPECL devices to QuickLogic Eclipse and Eclipse-II FPGAs

Posted: 22 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:FPGA? processor? programmable I/O?

Multiple I/O standards for processors, memories, and various applications have become commonplace and a requirement for many systems. The Eclipse family, which includes Eclipse, EclipsePlus, Eclipse-E, and Eclipse-II FPGAs, has addressed these changing system requirements with an I/O cell that consists of programmable I/Os as well as a cell structure consisting of three registersinput, output, and output enable. Banks of these programmable I/O are offered to address many of the new bus standards that are popular today.

Low voltage positive emitter coupled logic (LVPECL) is one of the prevalent I/O standards used in high-speed data communications and instrumentation systems as a reliable means to communicate with very low noise and low power consumption. The flexible I/O architecture in Eclipse devices allows for the implementation of LVPECL transmitters and receivers with the addition of external resistors.

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