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Custom PCI timing budgets for Spartan-3 generation FPGAs

Posted: 26 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:Spartan-3 FPGAs? custom PCI timing?

The PCI Local Bus Specification, Revision 3.0 (the PCI specification), defines two timing budgets. One timing budget is for use with 33 MHz operation, and the other timing budget is for use with 66 MHz operation. These two timing budgets define the I/O timing parameters for compliant 33 MHz and 66 MHz components.

In open systems, compliance with the PCI specification is a requirement to ensure interoperability. However, in embedded designs, it is possible to create custom timing budgets that enable system designers to do several things like Reduce total system cost by using less expensive devices.

The information presented in this application note is applicable to any embedded PCI implementation using Xilinx FPGA devices. The provided example applies this information to a design using Xilinx Spartan-3 Generation FPGAs with Xilinx LogiCORE PCI interfaces.

View the PDF document for more information.





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