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Eliminating I/O coupling effects when interfacing large-swing single-ended signals to user I/O pins on Spartan-3 Generation FPGAs

Posted: 26 May 2008 ?? ?Print Version ?Bookmark and Share

Keywords:Spartan-3 FPGAs? I/O coupling?

Spartan-3 Generation FPGAs support an exceptionally robust and flexible I/O feature set, such that the signaling requirements of most applications can easily be met. It is possible to program User I/O pins of these families to handle many different single-ended signal standards.

The standard single-ended signaling voltage levels are 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V. There are a number of applications for which it is desirable to receive signals with a greater voltage swing than User I/O pins ordinarily permit. The most common use case is receiving 5V signals on User I/O pins that are powered for use with one of the standard single-ended signaling levels listed above. In this application note, such signals are referred to as large-swing signals. Large-swing signals may be received by design or may be applied to the User I/O unintentionally from severe positive and/or negative overshoot. The cases of severe positive and/or negative overshoot can occur regardless of the programmed "direction" of a User I/O pin.

This application note describes solutions to receive large-swing signals by design. In one solution (and in the general case of severe positive and/or negative overshoot), parasitic leakage current between User I/O in differential pin pairs may occur, even though the User I/O pins are configured with single-ended I/O standards. This application note addresses the parasitic leakage current behavior.

View the PDF document for more information.

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