Using the FullFlex dual-port DDR interface

Cypress Semiconductor's FullFlex Dual-Port offers DDR mode to achieve the same data bandwidth of an SDR interface with half of the data pins, or twice the data bandwidth with the same amount of pins. In many cases, the number of IO pins affects device cost. One example of this is an FPGA. In this case, using the DDR interface to achieve the desired bandwidth is a preferred solution. Since DDR needs tighter timing control from the system design, the FullFlex Dual-Port device family also provides the Echo Clocks to ease the PCB design. By using the Echo Clocks to latch data, there will be dedicated clocks running along with the data for both READ and WRITE paths. This allows skews between the clock and data traces to be set for maximum benefit. This way the timing constraint on a PCB trace will be only relying on the trace length mismatch between the input clock and Write data for a WRITE operation, and mismatch between Echo Clock and Read data for a READ operation. This eliminates the operating speed dependency on the absolute distance between the controller and Dual-Port devices. Thus, maximum speed and better performance can be achieved for the system.

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