ST embraces 65nm process for SPEAr customizable chip

STMicroelectronics introduces a new member of its SPEAr family of configurable SoC ICs. Manufactured in low-power 65nm process technology, the new SPEAr Basic device addresses a wide variety of embedded applications, including entry-level printers, fax machines, digital photo frames, VoIP and other equipment.

The configurable SoC integrates an advanced ARM926EJ-S processor core with two16k memory caches, running at 333MHz, for data and instructions and up to 300,000 gates (ASIC-equivalent) of embedded configurable logic. It provides memory interfaces supporting LP-DDR and DDR2 memories and a large connectivity-IP portfolio, including Fast-IrDA interface, Ethernet MAC, three USB2.0 ports with embedded PHYs, UART, SPI, I2C, up to 102 fully programmable GPIOs and a total of 72 Kbytes of SRAM and 32 Kbytes of Boot ROM.

Exemplary printing performance is enabled through a full set of image-pipeline accelerators, from color-space conversion to raster-file generation, a rotation engine, a hardware JPEG codec, an LCD controller (up to 1024 x 768, 24bit per pixel) and a SDIO/MM card interface..

Additional features include a 10bit A/D converter, a crypto accelerator based on ST's proprietary C3 IP, a flexible static memory controller (NOR/NAND flash and SRAM), time-division multiplexing(TDM) and serial link and interrupt (SLIC) controllers and a camera interface, providing unprecedented scale of integration and flexibility.

The SPEAr Basic comes complete with an evaluation board that allows quick and easy setup, design and testing of the devices. Using the SPEAr Plus600 development kit and its external FPGA, which mirrors the SoC's internal configurable logic block, designers can proceed with software and hardware development without waiting for final validation.

Samples are available now, with volume production set to start by the end of Q3. The SPEAr Basic is priced at $6, in quantities above 20,000 pieces.